mc68hc11c0 Freescale Semiconductor, Inc, mc68hc11c0 Datasheet - Page 7

• Manufacturer Part Number: mc68hc11c0
• Description: 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

2 Operating Modes
2.1 Expanded Mode
CONFIG — System Configuration Register
Bits [7:6] — Not implemented
RWMC — Read/Write Strobe Mode Control
Bits [4:3] — Not implemented
NOCOP — COP Watchdog Timer Disable
MC68HC11C0
MC68HC11C0TS/D
RESET:
The MC68HC11C0 has four modes of operation. These modes directly affect the address space and
the memory map differs for each of them. Refer to the memory map diagram and the following para-
graphs.
In expanded mode, the MCU can access the full 64-Kbyte address space. The space includes the same
on-chip memory addresses used for single-chip mode as well as addresses for external peripherals and
memory devices. The 256-byte block of RAM is accessible in expanded mode but is disabled after re-
set. To enable RAM in expanded mode, set the RAMON bit in the CONFIG register. Vectors are fetched
from external locations $FFC0–$FFFF. The expansion bus consists of sixteen address lines (AD-
DR[15:0]) and eight data lines (DATA[7:0]). The read/write (R/W), read (RD), write (WR) and address
strobe (AS) signals are outputs that reflect the state of the internal data bus and are used to control the
direction of data on the data bus. The low-order address lines and the 8-bit data bus are time multi-
plexed on the same pins. During the first half of each bus cycle address information is present. During
the second half of each bus cycle the pins become the bidirectional data bus. AS is an active-high latch
enable signal for an external address latch. Address information is allowed through the transparent latch
while AS is high and is latched when AS drives low. The address, R/W, and AS signals are active and
valid for all bus cycles, including accesses to internal memory locations. The E-clock signal (E) is used
to enable external devices to drive data onto the internal data bus during the second half of a read bus
cycle (E clock low). Unlike other M68HC11 devices, the MC68HC11C0 inverts the E clock signal before
driving it out of the chip. R/W controls the direction of data transfers. R/W drives low when data is being
written to the data bus. R/W will remain low during consecutive data bus write cycles, such as when a
double-byte store occurs. Notice that the write enable signal for an external memory is the NAND of the
inverted E clock and the inverted R/W signal. Refer to the example diagram of address and data demul-
tiplexing. A more efficient method of controlling data on the bus can be employed by use of the RD and
the WR signals. Setting the RWMC bit in the CONFIG register causes the RD and the WR signals to be
driven out of the chip instead of E and R/W. RD asserts while a data bus read cycle is in progress. WR
asserts while a data bus write cycle is in progress.
In single-chip and expanded modes (SMOD = 0), CONFIG can only be written once. In special test
modes (SMOD = 1), CONFIG can be written any time. Changes do not take effect until the first cycle of
the instruction following the write to CONFIG.
Always read zero
Always read zero
Refer to 6 Resets and Interrupts .
0 = R/W is driven out of the chip
1 = RD and WR are driven out of the chip
Bit 7
—
0
—
6
0
Freescale Semiconductor, Inc.
RWMC
For More Information On This Product,
5
0
Go to: www.freescale.com
—
4
0
—
3
0
NOCOP RAMON
2
0
1
0
$003F
Bit 0
—
0
MOTOROLA
7