mc68hc11c0 Freescale Semiconductor, Inc, mc68hc11c0 Datasheet - Page 8

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mc68hc11c0

Manufacturer Part Number
mc68hc11c0
Description
8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
RAMON — RAM Enable
Bit 0 — Not implemented
2.2 Single-Chip Mode
2.3 Bootstrap Mode
8
MOTOROLA
Refer to 3 On-Chip Memory .
Always reads zero
In single-chip operating mode, the MC68HC11C0 is a stand-alone microcontroller with no external ad-
dress or data bus. External address and data lines are disabled. Bootloader ROM appears in the mem-
ory map at locations $BC00–$BFFF and $FC00–$FFFF. Since there is no external address or data bus,
the user must make certain that the RAM contains valid code before entering single-chip mode. The
register block is initially located at $0000 and can be remapped to any 1-Kbyte boundary. RAM is initially
located at $0400–$04FF and can be remapped to any 1-Kbyte boundary. Vectors are fetched internally
from locations $FFC0–$FFFF. Refer to the memory map diagram.
Bootstrap mode allows special-purpose programs to be entered into internal RAM. This mode is entered
by resetting to special test mode and then clearing the MDA bit in HPRIO register. When this mode is
selected, a 1024-byte bootstrap ROM becomes present in the memory map. Reset and interrupt vectors
NOTE: Use of the RD and
WR signals instead of E and
R/W will eliminate the need
for the external inverters and
NAND gate.
MC68HC11C0
ADDR3/DATA3
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR2/DATA2
ADDR0/DATA0
ADDR1/DATA1
ADDR13
ADDR15
ADDR14
ADDR12
ADDR10
ADDR11
R/W/WR
ADDR9
ADDR8
Freescale Semiconductor, Inc.
E/RD
For More Information On This Product,
AS
Figure 4 Address/Data Demultiplexing
Go to: www.freescale.com
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
LE
MC54/74HC373
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q0
MC68HC11C0TS/D
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
WE
MC68HC11C0

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