mc68hc11c0 Freescale Semiconductor, Inc, mc68hc11c0 Datasheet - Page 67

• Manufacturer Part Number: mc68hc11c0
• Description: 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

SCDR — SCI Data Register
10.2 Serial Peripheral Interface (SPI)
MC68HC11C0
MC68HC11C0TS/D
RESET:
Receive and transmit are double buffered. Reads access the receive data buffer, and writes access the
transmit data buffer. When the M bit in SCCR1 is set, R8 and T8 in SCCR1 store the ninth bit in receive
and transmit data characters.
The SPI allows the MCU to communicate synchronously with peripheral devices and other micropro-
cessors. When configured as a master, data transfer rates can be as high as one-half the E clock rate
(1 Mbit per second for a 2 MHz bus frequency). When configured as a slave, data transfers can be as
fast as the E clock rate (2 Mbit per second for a 2 MHz bus frequency).
During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes
shifting and sampling of the information on the two serial data lines. A slave select line allows individual
selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activ-
ities. On a master SPI device, the select line can optionally be used to indicate a multiple master bus
contention.
The central element in the SPI system is the block containing the shift register and the read data buffer.
The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that new data for transmission cannot be written to the shifter until the previous transfer is com-
plete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept
a second serial character. As long as the first character is read out of the read data buffer before the
next serial character is ready to be transferred, no overrun condition occurs. A single MCU register ad-
dress is used for reading data from the read data buffer and for writing data to the shifter. Refer to the
SPI block diagram.
Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI
control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active
high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA)
control bit selects one of two different transfer formats.
The SPI system external pins are implemented as an alternate function of port D pins. In addition to the
port D data direction register (DDRD), the port D I/O control register (DIOCTL) determines which func-
tions are performed by port D pins. The port D open drain mode (DODM) register controls the driver
type for each port D pin configured as an output. Refer to the descriptions of PORTD, DDRD, DIOCTL,
and DODM registers.
R7/T7
Bit 7
U
R6/T6
U
6
Freescale Semiconductor, Inc.
For More Information On This Product,
R5/T5
U
5
Go to: www.freescale.com
R4/T4
U
4
R3/T3
U
3
R2/T2
U
2
R1/T1
U
1
R0/T0
Bit 0
$002F
U
MOTOROLA
67