mc68hc705j1avs Freescale Semiconductor, Inc, mc68hc705j1avs Datasheet - Page 42

• Manufacturer Part Number: mc68hc705j1avs
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Memory
Technical Data
SWAIT — Stop-to-Wait Conversion Bit
SWPDI — Software Pulldown Inhibit Bit
PIRQ — Port A External Interrupt Bit
LEVEL —External Interrupt Sensitivity Bit
COPEN — COP Enable Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 t
exiting halt mode.
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
The LEVEL bit controls external interrupt triggering sensitivity.
The COPEN bit enables the COP watchdog.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Halt mode enabled
0 = Halt mode not enabled
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
1 = COP watchdog enabled
0 = COP watchdog disabled
Go to: www.freescale.com
Memory
MC68HC705J1A — Rev. 4.0
cyc
occurs after