mc68hc705j1avs Freescale Semiconductor, Inc, mc68hc705j1avs Datasheet - Page 94

• Manufacturer Part Number: mc68hc705j1avs
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Parallel Input/Output (I/O) Ports
6.4.3 Pulldown Register B
Technical Data
NOTE:
Address:
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port B pins.
Pulldown register B (PDRB) inhibits the pulldown devices on port B pins
programmed as inputs.
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with disabled pulldown devices.
PDIB[7:0] — Pulldown Inhibit B Bits
Reset:
1. Writing affects the data register, but does not affect input.
Read:
Write:
PDIB[7:0] disable the port B pulldown devices. Reset clears
PDIB[7:0].
Freescale Semiconductor, Inc.
Data Direction Bit
For More Information On This Product,
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
$0011
Bit 7
0
1
Parallel Input/Output (I/O) Ports
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Figure 6-9. Pulldown Register B (PDRB)
= Unimplemented
6
Table 6-2. Port B Pin Operation
PDIB5
Input, high-impedance
5
0
I/O Pin Mode
Output
PDIB4
4
0
Table 6-2
PDIB3
3
0
summarizes the operation
MC68HC705J1A — Rev. 4.0
PDIB2
Accesses to Data Bit
Read
Latch
Pin
2
0
PDIB1
1
0
Latch
Write
Latch
PDIB0
(1)
Bit 0
0