mc68hc705j1avs Freescale Semiconductor, Inc, mc68hc705j1avs Datasheet - Page 91

• Manufacturer Part Number: mc68hc705j1avs
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

6.3.3 Pulldown Register A
MC68HC705J1A — Rev. 4.0
NOTE:
Address:
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port A pins.
Pulldown register A (PDRA) inhibits the pulldown devices on port A pins
programmed as inputs.
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port A pins as inputs with disabled pulldown devices.
PDIA[7:0] — Pulldown Inhibit A Bits
Reset:
1. Writing affects the data register but does not affect input.
Read:
Write:
PDIA[7:0] disable the port A pulldown devices. Reset clears
PDIA[7:0].
Freescale Semiconductor, Inc.
Data Direction Bit
For More Information On This Product,
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
PDIA7
$0010
Bit 7
0
0
1
Parallel Input/Output (I/O) Ports
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Figure 6-5. Pulldown Register A (PDRA)
= Unimplemented
PDIA6
6
0
Table 6-1. Port A Pin Operation
PDIA5
Input, high-impedance
5
0
I/O Pin Mode
Output
PDIA4
4
0
Table 6-1
PDIA3
3
0
summarizes the operation
Parallel Input/Output (I/O) Ports
PDIA2
Accesses to Data Bit
Read
Latch
Pin
2
0
PDIA1
1
0
Technical Data
Latch
Write
Latch
PDIA0
(1)
Bit 0
Port A
0