adm6999ux Infineon Technologies Corporation, adm6999ux Datasheet
adm6999ux
Available stocks
Related parts for adm6999ux
adm6999ux Summary of contents
Page 1
...
Page 2
Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
Page 3
Mb/s Single Chip Ethernet Switch Controller Revision History: 2005-11-25, Rev. 1.42 Previous Version: Page/Date Subjects (major changes since last revision) 2002-08 Rev. 0.1: First Infineon ADMtek Co Ltd version 2002-09 Rev. 1.0: Remove Preliminary word 2002-12 Rev. ...
Page 4
Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of Figures Figure 1 ADM6999U/UX’s Application 9 Figure 2 ADM6999U/UX 128 Pin Diagram 10 Figure 3 100Base-X Module 18 Figure 4 Serial LED Interface 27 Figure 5 Scan LED Interface 28 Figure 6 Router old architecture 44 Figure 7 ...
Page 7
List of Tables Table 1 Abbreviations for Pin Type 11 Table 2 Abbreviations for Buffer Type 11 Table 3 ADM6999U/UX 128 Pin Descriptions 12 Table 4 Port Rising/Falling Threshold 25 Table 5 LED Display 27 Table 6 LED Corresponding Interface ...
Page 8
... Mbps TX/FX plus one 1.6G Expansion port Ethernet switch controller with all ports supporting 10/100 Mbps Full/Half duplex switch function. The ADM6999U/UX is intended for applications to stand alone the bridge for low cost 16 Port Switch. The ADM6999UX is the environmentally friendly “green” package version. ADM6999U/UX provides most advanced functions such as: 802.1p (Q.O.S.ADM6999U/UX), 802.1q (VLAN), Port MAC Address Locking, Management, Port Status, TP Auto-MDIX, 25M Crystal & ...
Page 9
Applications ADM6999U/UX in 128-pin PQFP: • 16-port switch Figure 1 ADM6999U/UX’s Application Data Sheet 1.6Gbps Expansion bus ADM6999U 8 10/100 MDIX TX/FX 9 ADM6999U/UX Data Sheet Introduction ADM6999U 8 10/100 MDIX TX/FX Rev. 1.42, 2005-11-25 ...
Page 10
Input and Output Signals This chapter describes Pin Diagram and Pin Description. 2.1 Pin Diagram ERXD4 GNDO VCC3O ERXD5 ERXD6 ERXD7 LEDCLK (ANEN) (OE2) VCCIK GNDIK VCCPLL GNDPLL CONTROL VREF GNDBIAS RTX VCCBIAS VCCA2 TXP0 TXN0 ...
Page 11
Pin Type and Buffer Type Abbreviations Standardized abbreviations: Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. AO Output. ...
Page 12
Pin Description Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. Twisted Pair Interface 126 RXP0 2 RXP1 11 RXP2 15 RXP3 24 RXP4 28 RXP5 37 RXP6 41 RXP7 127 RXN0 1 RXN1 12 RXN2 14 ...
Page 13
Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 63 ETXD0 GFCEN 61 ETXD1 60 ETXD2 59 ETXD3 55 ETXD4 54 ETXD5 51 ETXD6 50 ETXD7 62 P7FX ETXD8 66 ETXEN PHYAS0 Data Sheet Pin Buffer Function Type ...
Page 14
Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 74 ERXD0 100 ERXD1 101 ERXD2 102 ERXD3 103 ERXD4 106 ERXD5 107 ERXD6 108 ERXD7 68 ERXD8 73 ERXDV 78 ECOL 77 ECRS 58 ETXCLK 72 ERXCLK LED ...
Page 15
Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 98 LED0 97 LED1 96 LED2 95 LED3 92 LED4 91 LED5 90 LED6 89 LED7 92 Dual Color EEPROM/Management Interface 84 EEDO 80 EECS 81 EECK XOVEN 79 ...
Page 16
Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 113 XI 114 XO 49 TEST Chip Configuration 46 ALERT Power/Ground 3, 10, 16, 23, GNDA 29, 36, 42, 125 6, 7, 19, 20, VCCA2 32, 33, 45, 122 ...
Page 17
Descriptions This chapter provides Functional Description, 10/100M PHY Block Description, Memory Block Description, Switch Functional Description, EEPROM Content and EEPROM Access Description. 3.1 Functional Description The ADM6999U/UX integrates eight 100Base-X physical sub-layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, ...
Page 18
Stream decoder block RXD[1:0] RXD[3:0] BP_ALIGN CRSDV CRS RXDV RXER COL TXCLK TXEN TXER TXEN TXD[3:0] BP_4B5B TXD[1:0] Figure 3 100Base-X Module 3.2.2.1 A/D Converter High performance A/D converter with 125 MHz sampling rate converts signals received on RXP/RXN ...
Page 19
Data De-scrambling The de-scrambler acquires synchronization with the data stream by recognizing idle bursts more bits and locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the ...
Page 20
Carrier Sense Carrier sense (CRS) for 100Mbits/s operation is asserted upon the detection of two noncontiguous zeros occurring within any 10-bit boundary of the received data stream. The carrier sense function is independent of symbol alignment. In switch mode, ...
Page 21
Module The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loop back, jabber, wave shaper, and link integrity functions, as defined in the standard. The ADM6999U/UX 10Base-T module is comprised of the ...
Page 22
The receiving squelch threshold level can be lowered for use in longer cable applications. This is achieved by setting bit 10 of register address 11 3.2.5 Carrier Sense Carrier Sense (CRS) is asserted due ...
Page 23
Memory Block Description ADM6999U/UX builds in 768K bits memory inside. Memory buffer is divided as two blocks. One is MAC addressing table and another one is data buffer. MAC address Learning Table size is 2048 entries with each entry ...
Page 24
If the UNICAST address and the address was not found, the ADM6999U/UX treats multicast packet and forwards across the bridge the Multicast address, the packet is forwarded across ...
Page 25
Broadcast Storm Filter If Broadcast Storming filter is enable, the broadcast packets over the rising threshold within 50 ms will be discarded by the threshold setting. See EEPROM Reg.10 Broadcast storm mode after initial: Time interval The ...
Page 26
VLAN Group Mapping Register. EEPROM register 013 register to define VLAN group. Users can define each port as Tag port or Untag port by Configuration register Bit 4. The operation of packet between Tag port and Untag port can ...
Page 27
Table 5 LED Display Configuration LED Mode ADM6999U 8+1 EBus 1: serial interface0: /UX scan interface 3.4.6.1 Serial LED Interface A two pins interface, LEDDATA and LEDCLK, provides external shift register to capture the LED status indicated by the ADM6999U/UX. ...
Page 28
Figure 5 Scan LED Interface Table 6 LED Corresponding Interface Configuration ADM6999U/UX 8+1MII ADM6999U/UX 8+1 GPSI 8+1 RMII Data Sheet LEDMODE Interface utilized 1: dual color Serial Interface. Totally two pins, LEDCLK, and 0: single color LEDDATA are used to ...
Page 29
EEPROM Content EEPROM provides ADM6999U/UX many options setting such as: • Port Configuration: Speed, Duplex, Flow Control Capability and Tag/Untag • VLAN & TOS Priority Mapping • Broadcast Storming rate and Trunk • Fiber Select, Auto MDIX select • ...
Page 30
Table 7 EEPROM Register Map Register Bit 15-8 18 VLAN 5 outbound Port Map H VLAN 11 outbound Port Map 19 VLAN 6 outbound Port Map H VLAN 13 outbound Port Map 1A VLAN 7 outbound Port Map H VLAN ...
Page 31
EEPROM Registers Overview Table 8 Registers Address SpaceRegisters Address Space Module Base Address EEPROM 00 H Table 9 Registers Overview Register Short Name Register Long Name SR Signature Register PCR_0 Port Configuration Register 0 PCR_1 Port 1 Configuration Register ...
Page 32
Table 9 Registers Overview (cont’d) Register Short Name Register Long Name PBTCR_P01 Port Buffer Threshold Control Reg. P0, P1 PBTCR_P23 Port Buffer Threshold Control Reg. P2, P3 PBTCR_P45 Port Buffer Threshold Control Reg. P4, P5 PBTCR_P67 Port Buffer Threshold Control ...
Page 33
Table 10 Register Access Types (cont’d) Mode Symbol Description HW latch_on_reset lor rw register, value is latched after first clock cycle after reset Read/write rwsc Register is used as input for the hw, the self clearing register will be cleared ...
Page 34
Configuration Registers Register 0x09h bit5 is not effective on disable port. User can disable port by VLAN. PCR_0 Port Configuration Register 0 Field Bits Type ANE 13:10 rw PBPN 9 ...
Page 35
Field Bits Type Table 12 PCR_x Registers Table Register Short Name Register Long Name PCR_1 Port 1 Configuration Register PCR_2 Port 2 Configuration Register PCR_3 ...
Page 36
Gigabit Port Configuration Register GPCR Gigabit Port Configuration Register Field Bits Type CBTC 15: MII 7:0 rw Data Sheet Offset 0A H Description Cascade Buffer Threshold Control. Casecade buffer threshold control. These bits ...
Page 37
Configuration Register CR Configuration Register Field Bits Type Res 14 ro Res 13 ro Res 12 Res 5 ro Res 4:0 ro Data Sheet Offset 0B H Description Disable Far_End_Fault ...
Page 38
VLAN Priority Map Register VLAN_PMR VLAN Priority Map Register Field Bits Type V7 15: 13: 11 1:0 rw 00: low priority queue. ...
Page 39
TOS Priority Map Register TOS_PMR TOS Priority Map Register Field Bits Type V7 15: 13: 11 1:0 rw 00: low priority queue. ...
Page 40
Ethernet Packet from Layer 2 Preamble/SFD Destination (6 bytes) – Byte 0~5 • VLAN Packet ADM6999U/UX will check packet byte 12 &13. If byte[12:13] = 8100h then this packet is a VLAN packet. Tag Protocol TD 8100 Tag Control Information ...
Page 41
Miscellaneous Configuration Register 0 MCR_0 Miscellaneous Configuration Register 0 Field Bits Type Res 15: 13:12 rw DM1 11:10 rw DM0 9 Res 6 ro Res 5 ro XCRC 4 rw Res 3 ro BSE ...
Page 42
Table 13 Per Port Rising Threshold 00 All 100TX Disable Not All 100TX Disable Table 14 Per Port Falling Threshold 00 All 100TX Disable Not All 100TX Disable Table 15 Drop Scheme for each Queue Discard Mode/ 00 Utilization TBD ...
Page 43
VLAN Mode Select Register VLAN_MSR VLAN Mode Select Register Field Bits Type Res 15: Res 8 ro Res 7 Res 3:0 ro Below is Bit4, 5 ...
Page 44
Table 16 ADM6996 Port Mapping with ADM6999U/UX ADM6996 Port0 – Port1 – Port2 – Port3 Port4 Port5 MII Below is Router old architecture. The disadvantages of this are: 1. WAN port only support 10M Half-Duplex and non-MDIX function. 2. Need ...
Page 45
Figure 7 New architecture by using ADM6999U/UX serial chip VLAN function New Router application works well on normal application. If user’s ISP vendor (cable modem) lock Registration Card’s ID then Router CPU must send this Lock Registration Card’ ...
Page 46
WAN to CPU Traffic. ADM6999U/UX WAN traffic to CPU only. Traffic to CPU is Tag packet with VID = 2. CPU can check VID to distinguish LAN traffic or WAN traffic. 3. CPU to LAN Packet. ADM6999U/UX CPU Packet ...
Page 47
Field Bits Type ML3 3 rw ML2 2 rw ML1 1 rw ML0 0 rw Notes 1. Bit [8:0]: Port Locking enable. Learn one MAC ID when enable. 1/enable. 0/disable. 2. Bit[15]: Half Duplex excessive collision (16) drop packet enable. ...
Page 48
Field Bits Type Select the VLAN group ports is to set the corresponding bits to 1. VLAN Mapping Table Registers 0 32 VLAN Group: See Register 2C VLAN_MTR VLAN Mapping Table Registers Field Bits ...
Page 49
Table 17 VLAN_MTR_x Registers Table Register Short Name Register Long Name VLAN_MTR_1 VLAN Mapping Table Register 1 VLAN_MTR_2 VLAN Mapping Table Register 2 VLAN_MTR_3 VLAN Mapping Table Register 3 VLAN_MTR_4 VLAN Mapping Table Register 4 VLAN_MTR_5 VLAN Mapping Table Register ...
Page 50
Port Buffer Threshold Control Registers P0, P1 PBTCR_P01 Port Buffer Threshold Control Reg. P0, P1 Field Bits Type Port_1 15:8 rw Port_0 7:0 rw Port Buffer Threshold Control Register P2, P3 PBTCR_P23 Port Buffer Threshold Control Reg. P2, P3 Field ...
Page 51
Port Buffer Threshold Control Register P4, P5 PBTCR_P45 Port Buffer Threshold Control Reg. P4, P5 Field Bits Type Port_5 15:8 rw Port_4 7:0 rw Port Buffer Threshold Control Register P6, P7 PBTCR_P67 Port Buffer Threshold Control Reg. P6, P7 Field ...
Page 52
Total Buffer Threshold Control Register TBTCR Total Buffer Threshold Control Register Field Bits Type FQMC 15 rw FQM 14 rw TBTC 13:8 rw PBTC 7:0 rw Dynamic threshold management: Bit[13]: The add bit. Bit[12:8]: The offset bits.When Bit[13 ...
Page 53
Port0, 1 PVID bit11~4 Configuration Register PVID11_4_CR_P01 Port0, 1 PVID bit11~4 Configuration Register Field Bits Type Port_1 15:8 rw Port_0 7:0 rw Data Sheet Offset 28 H Description Port1 PVID bit 11~4 These 8 bits combine with register 02 00 ...
Page 54
Port2, 3 PVID bit11~4 Configuration Register PVID11_4_CR_P23 Port2, 3 PVID bit11~4 Configuration Register Field Bits Type Port_3 15:8 rw Port_2 7:0 rw Data Sheet Offset 29 H Description Port3 PVID bit 11~4 These 8 bits combine with register 04 00 ...
Page 55
Port4, 5 PVID bit 11~4 Configuration Register PVID11_4_CR_P45 Port4, 5 PVID bit 11~4 Configuration Register Field Bits Type Port_5 15:8 rw Port_4 7:0 rw Data Sheet Offset 2A H Description Port5 PVID bit 11~4 These 8 bits combine with register ...
Page 56
Port6, 7 PVID bit 11~4 Configuration Register PVID11_4_CR_P67 Port6, 7 PVID bit 11~4 Configuration Register Field Bits Type Port_7 15:8 rw Port_6 7:0 rw Port8 PVID bit 11~4 and VLAN Group Shift Bits Configuration Register PVID11_4_VLAN_CR P8 PVID bit 11~4/VLAN ...
Page 57
Field Bits Type SAF 15: SHIFT 10:8 rw Data Sheet Description Special Address Forwarding IEEE 802.3 reserved DA forward or drop police 1101 , default H Bit[15] Control reserved MAC (0180C2000010-0180C20000FF Discard B 1 ...
Page 58
Field Bits Type Port_8 7:0 rw Data Sheet Description Expansion Port PVID bit 11~4 These 8 bits combine with register default H 58 ADM6999U/UX Data Sheet Descriptions Bit[13~10] as full 12 bit VID. H Rev. 1.42, 2005-11-25 ...
Page 59
EEPROM Access Description Customer can select ADM6999U/UX read EEPROM contents as chip setting or not. ADM6999U/UX will check the signature of EEPROM to decide read content of EEPROM or not. Table 18 RC & EEPROM Content Relationship RC CS ...
Page 60
The timing for writing to EEPROM is a little bit different. See below graph. Must be carefully when CS goes down after writting a command, SK must issue at least one clock. This is a difference between ADM6999U/UX with EEPROM ...
Page 61
TX/FX Interface 4.1 TP Interface TXP TXN ADM6999U RXP RXN Figure 10 TP Interface Transformer requirement: • TX/RX rate 1:1 • TX/RX central tap connect together to VCCA2. Users can change TX/RX pin for easy layout but do not ...
Page 62
TXP TXN ADM6999U RXP RXN Figure 11 FX Interface Data Sheet +3.3V 127 127 ADM6999U/UX Data Sheet TX/FX Interface +3. 3.3V Fiber Transceiver 1 GND_RX 2 RD VCC_RX VCC(3.3) ...
Page 63
DC Characteristics Table 19 Absolute Maximum Ratings Parameter Power Supply TX line driver PLL voltage Digital core voltage Input Voltage Output Voltage Storage Temperature Power Dissipation ESD Rating Table 20 Recommended Operating Conditions Parameter Power Supply TX line driver ...
Page 64
Serial Management 6.1 Serial Registers Map Table 22 Registers Address SpaceRegisters Address Space Module Base Address Serial 00 H Table 23 Registers Overview Register Short Name Register Long Name Chip_ID Chip Identifier Register PSR_0 Port Status 0 Register PSR_1 ...
Page 65
Table 23 Registers Overview (cont’d) Register Short Name Register Long Name TPC_8 Port 8 Transmit Packet Count TPBC_0 Port 0 Transmit Packet Byte Count TPBC_1 Port 1 Transmit Packet Byte Count TPBC_2 Port 2 Transmit Packet Byte Count TPBC_3 Port ...
Page 66
Table 24 Register Access Types (cont’d) Mode Symbol Description HW Read only ro Register is set by HW (register between input and output -> one cycle delay) Read virtual rv Physically, there is no new register, the input of the ...
Page 67
Field Bits Type ID 31 3:0 ro Port Status 0 Register PSR_0 Port Status 0 Register Field Bits Type FC_7 31 ro DS_7 30 ro SS_7 29 ro LUS_7 28 ro FC_6 27 ro DS_6 26 ro SS_6 ...
Page 68
Field Bits Type LUS_6 24 ro FC_5 23 ro DS_5 22 ro SS_5 21 ro LUS_5 20 ro FC_4 19 ro DS_4 18 ro SS_4 17 ro LUS_4 16 ro FC_3 15 ro DS_3 14 ro SS_3 13 ro LUS_3 ...
Page 69
Field Bits Type SS_2 9 ro LUS_2 8 ro FC_1 7 ro DS_1 6 ro SS_1 5 ro LUS_1 4 ro FC_0 3 ro DS_0 2 ro SS_0 1 ro LUS_0 0 ro Data Sheet Description Port 2 Speed Status ...
Page 70
Port Status 1 Register PSR_1 Port Status 1 Register Field Bits Type Res 31 2:1 ro LUS 0 ro Data Sheet Offset 02 H Description Reserved 0 , default H Expansion Flow ...
Page 71
Cable Broken Status Register CBSR Cable Broken Status Register Field Bits Type Res 31:24 ro CB_7 23 ro CBL_7 22:21 ro CB_6 20 ro CBL_6 19:18 ro CB_5 17 ro CBL_5 16:15 ro CB_4 14 ro CBL_4 13:12 ro CB_3 ...
Page 72
Field Bits Type Count_0 31:0 ro Other Port Registers have a similar structure as RPC_0; see Table 26 Port Registers RPC_x Register Short Name Register Long Name RPC_1 Port 1 Receive Packet Count RPC_2 Port 2 Receive Packet Count RPC_3 ...
Page 73
Table 26 Port Registers RPC_x Register Short Name Register Long Name TPBC_8 Port 8 Transmit Packet Byte Count CC_0 Port 0 Collision Count CC_1 Port 1 Collision Count CC_2 Port 2 Collision Count CC_3 Port 3 Collision Count CC_4 Port ...
Page 74
Over Flow Flag 0 Register OFFR_0 Over Flow Flag 0 Register Field Bits Type P8 17 lhsc P7 16 lhsc P6 15 lhsc P5 14 lhsc P4 13 lhsc P3 12 lhsc P2 11 lhsc P1 10 lhsc P0 9 ...
Page 75
Over Flow Flag 1 Register OFFR_1 Over Flow Flag 1 Register Field Bits Type P8 17 lhsc P7 16 lhsc P6 15 lhsc P5 14 lhsc P4 13 lhsc P3 12 lhsc P2 11 lhsc P1 10 lhsc P0 9 ...
Page 76
Over Flow Flag 2 Register OFFR_2 Over Flow Flag 2 Register Field Bits Type P8 17 lhsc P7 16 lhsc P6 15 lhsc P5 14 lhsc P4 13 lhsc P3 12 lhsc P2 11 lhsc P1 10 lhsc P0 9 ...
Page 77
Serial Interface Timing ADM6999U/UX serial chip internal counter or EEPROM access timing. • EESK: Similar as MDC signal • EDI: Similar as MDIO • ECS: Must keep low Device Opcode Preamble Start ...
Page 78
Preamble Figure 13 Serial Interface Timing Y • Preamble: At least 32 continuous “1” • Start bits) • Opcode bits, Reset command) • Device Address: Chip physical address as PHYAS[1:0] • Reset_type: Reset counter by port ...
Page 79
AC Characteristics 7.1 Power On Reset 0ms RC All Configuration Pins Figure 14 Power On Reset Table 27 Power On Reset Parameter RST Low Period Start of Idle Pulse Width 7.2 EEPROM Data Timing 0us EECS EESK tEWDD EEDO ...
Page 80
Table 28 EEPROM Data Timing (cont’d) Parameter EESK High Period EEDI to EESK Rising Setup Time EEDI to EESK Rising Hold Time EESK Falling to EEDO Output Delay Time 7.3 Expansion Bus Receive Signals Timing ERXCLK ERXD[7::0], ERXDV Figure 16 ...
Page 81
ETXCLK ETXD[7:0] ETXEN Figure 17 Expansion Bus Transmit Signals Timing Table 30 Expansion Bus Transmit Signals Timing Parameter Data Valid Delay after Rising ETXCLK 7.5 SMI Timing 0ns EESK EEDI Figure 18 SMI Timing Table 31 SMI Timing Parameter EESK ...
Page 82
Package ADM6999U/UX 128 Pin PQFP Outside Dimension Figure 19 ADM6999U/UX 128 Pin PQFP Outside Dimension Data Sheet 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12 ADM6999U/UX Data Sheet Package Rev. 1.42, 2005-11-25 ...
Page 83
References [1] [2] [3] [4] [5] [6] Data Sheet 83 ADM6999U/UX Data Sheet References Rev. 1.42, 2005-11-25 ...
Page 84
Terminology A B Data Sheet 84 ADM6999U/UX Data Sheet Terminology Rev. 1.42, 2005-11-25 ...
Page 85
Published by Infineon Technologies AG ...