adm6999ux Infineon Technologies Corporation, adm6999ux Datasheet - Page 17

• Manufacturer Part Number: adm6999ux
• Description: Adm6999u 9 Port 10/100 Mb/s Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

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This chapter provides Functional Description, 10/100M PHY Block Description, Memory Block Description, Switch
Functional Description, EEPROM Content and EEPROM Access Description.
3.1
The ADM6999U/UX integrates eight 100Base-X physical sub-layer (PHY), 100Base-TX physical medium
dependent (PMD) transceivers, eight complete 10Base-T modules, 8 port 100/10 switch controller, and one 1.6G
Expansion Port and memory into a single chip for both 10Mbits/s, 100Mbits/s Ethernet switch operations. It also
supports 100Base-FX operation through external fiber-optic transceivers. The device is capable of operating in
either Full Duplex mode or Half-Duplex mode in 10Mbits/s and 100Mbits/s. Operational modes can be selected by
hardware configuration pins, software settings of management registers, or determined by the on-chip auto
negotiation logic.
The ADM6999U/UX consists of three major blocks:
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3.2
The 100Base-X section of the device implements the following functional blocks:
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The 100Base-X and 10Base-T sections share the following functional blocks:
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3.2.1
The ADM6999U/UX implements 100Base-X compliant PCS, PMA and 100Base-TX compliant TP-PMD as
illustrated in
flexibility for various applications. 100Mbits/s PHY loop back is included for diagnostic purpose.
3.2.2
The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s received
data stream. The ADM6999U/UX implements the 100Base-X receiving state machine diagram as given in
ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s received data stream may originate from the on-chip
twisted-pair transceiver in a 100Base-TX application. Alternatively, the received data stream may be generated by
an external optical receiver as in a 100Base-FX application.
The receiver block consists of the following functional sub-blocks:
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Data Sheet
10/100M PHY Block
Switch Controller Block
Built-in 12Kx64 SSRAM
100Base-X physical coding sub-layer (PCS)
100Base-X physical medium attachment (PMA)
Twisted-pair transceiver (PMD)
Clock synthesizer module
MII Registers
IEEE 802.3u auto negotiation
A/D Converter
Adaptive Equalizer and timing recovery module
NRZI/NRZ and serial/parallel decoder
De-scrambler
Symbol alignment block
Symbol Decoder
Collision Detect Block
Carrier sense Block
Figure
Descriptions
Functional Description
10/100M PHY Block Description
100Base-X Module
100Base-X Receiver
3. Bypass options for each of the major functional blocks within the 100Base-X PCS provide
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Rev. 1.42, 2005-11-25
ADM6999U/UX
Data Sheet
Descriptions