adm6999ux Infineon Technologies Corporation, adm6999ux Datasheet - Page 21

• Manufacturer Part Number: adm6999ux
• Description: Adm6999u 9 Port 10/100 Mb/s Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

3.2.4
The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,
heartbeat, loop back, jabber, wave shaper, and link integrity functions, as defined in the standard.
The ADM6999U/UX 10Base-T module is comprised of the following functional blocks:
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3.2.4.1
The ADM6999U/UX 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In
half-duplex mode, the ADM6999U/UX functions as an IEEE 802.3 compliant transceiver with fully integrated
filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during
transmitting and receiving. In full duplex mode the ADM6999U/UX can simultaneously transmit and receive data.
3.2.4.2
Data encoding and transmission begin when the transmission enable input (TXEN) goes high and continues as
long as the transceiver is in good link state. Transmission ends when the transmission enable input goes low. The
last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0.
Decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separate the
Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when
no more mid bit transitions are detected. Within one and half bit times after the last bit, carrier sense is de-asserted.
3.2.4.3
The ADM6999U/UX integrates all the required signal conditioning functions in its 10Base-T block such that
external filters are not required. Only one isolation transformer and impedance matching resistors are needed for
the 10Base-T transmitting and receiving interface. The internal transmitting filtering ensures that all the harmonics
in the transmission signal are attenuated properly.
3.2.4.4
The smart squelch circuit is responsible for determining when valid data is present on the differential receiption.
The ADM6999U/UX implements an intelligent receiving squelch on the RXP/RXN differential inputs to ensure that
impulse noise on the receiving inputs will not be mistaken for a valid signal. The squelch circuitry employs a
combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to
determine the validity of data on the twisted-pair inputs.
The signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the
squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is
overcome correctly, the opposite squelch level must then be exceeded within 150ns. Finally, the signal must
exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected.
Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder
of the circuitry that valid data is present.
Valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns,
indicating end of packet. Once good data has been detected, the squelch levels are reduced to minimize the effect
Data Sheet
Manchester encoder and decoder
Collision detector
Link test function
Transmit driver and receiver
Serial and parallel interface
Jabber and SQE test functions
Polarity detection and correction
10Base-T Module
Operation Modes
Manchester Encoder/Decoder
Transmit Driver and Receiver
Smart Squelch
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Rev. 1.42, 2005-11-25
ADM6999U/UX
Data Sheet
Descriptions