peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 139

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

PEB 20532
PEF 20532
Register Description (FIFOH)
Receive FIFO (RFIFO)
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus
mode only 16-bit accesses to RFIFO are allowed. Only for a frame with odd byte count
the last access can be an 8-bit access.
The size of the accessible part of RFIFO is determined by programming the RFIFO
threshold level in bit field CCR3H.RFTH(1:0). If the HDLC/PPP protocol machine is
selected, the threshold can be adjusted to 32 (reset value), 16, 4 or 2 bytes. With the
ASYNC and BISYNC protocol machines following threshold levels can be selected: 1
(reset value), 4, 16 or 32 bytes.
• Interrupt Controlled Data Transfer (GMODE.EDMA=’0’)
Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF
or an RME interrupt (see
ISR0
register). The address provided during an RFIFO read
access is not incremental; it is always 10
for channel A or 60
for channel B.
H
H
RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is
reached. The message is not yet complete. A fix number of bytes, dependent from the
threshold level, has to be read.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL,
RBCH
registers.
The content of the RFIFO is released by issuing the “Receive Message Complete”
command (CMDRH.RMC).
• DMA Controlled Data Transfer (GMODE.EDMA=’1’)
If DMA operation is enabled, the SEROCCO-M autonomously requests data transfer by
asserting the DRR line to the external DMA controller. The DRR line remains active until
the beginning of the last receive data byte/word transfer. For a detailed decsription of the
external DMA interface operation refer to
“External DMA Controller Support” on
Page
79.
Transmit FIFO (XFIFO)
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus
mode only 16-bit accesses to XFIFO are allowed. Only for a frame with odd byte count
the last access must be an 8-bit access.
• Interrupt Controlled Data Transfer (GMODE.EDMA=’0’)
Following an XPR (or an ALLS) interrupt, up to 32 bytes/16 words of new transmit data
can be written into the XFIFO. Transmit data can be released for transmission with an
XTF command. The address provided during an XFIFO write access is not incremental;
it is always 10
for channel A or 60
for channel B.
H
H
• DMA Controlled Data Transfer (GMODE.EDMA=’1’)
Data Sheet
5-139
2000-09-14