peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 97

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

• Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1
The isochronous mode uses the asynchronous character format. However, each data bit
is only sampled once (no oversampling).
In clock modes 0 ,1 and 4, the input clock has to be externally phase locked to the data
stream. This mode allows much higher transfer rates. Clock modes 3b and 7b are not
recommended due to difficulties with bit synchronization when using the internal baud
rate generator.
In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct
synchronization of the DPLL is achieved if there are enough edges within the data
stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester)
is used.
4.4.2.3
If the receiver is enabled, received data is stored in the SCC receive FIFO (the LSB is
received first). Moreover, the CD input may be used to control data reception. Character
length, number of stop bits and the optional parity bit are checked. Storage of parity bits
can be disabled. Errors are indicated via interrupts. Additionally, the character specific
error status (framing and parity) can optionally be stored in the SCC receive FIFO.
Filling of the the SCC receive FIFO is controlled by
• a programmable threshold level (bit field ’RFTH’ in register CCR3H),
• the selected data format (bit ’RFDF’ in register CCR3H),
• the parity storage selection (bit ’DPS’ in register CCR3H),
• detection of the programmable Termination Character (bit ’TCDE’ in register
Additionally, the time-out event interrupt as an optional status information indicates that
a certain time (refer to register TOLEN) has elapsed since the reception of the last
character.
4.4.3
The selection of asynchronous or isochronous operation has no further influence on the
transmitter. The bit clock rate is solely a dividing factor for the selected clock source.
Transmission of the contents of the SCC transmit FIFO starts after the ’XF’ command is
issued (the LSB is sent out first). Further data is requested by an ’XPR’ interrupt (or by
DMA). The character frame for each character, consisting of start bit, the character itself
with defined character length, optionally generated parity bit and stop bit(s) is
assembled.
After finishing transmission (indicated by the ‘ALLS’ interrupt), IDLE sequence (logical
‘1’) is transmitted on pin TxD.
Data Sheet
or Manchester encoding (register
and bit field ’TC’ in register TCR).
Storage of Receive Data
Data Transmission
CCR0L
97
/
CCR0H
bit fields ’CM’ and ’SC’).
Detailed Protocol Description
PEB 20532
PEF 20532
2000-09-14
CCR3L