peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 151

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 21
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 22
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
Power
VIS
VIS
VIS
PU
PU
PU
7
7
CCR0L
Channel Configuration Register 0 (Low Byte)
CCR0H
Channel Configuration Register 0 (High Byte)
PSD
PSD
PSD
6
6
read/write
00
Channel A
16
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
17
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
misc.
Line Coding
SC(2:0)
SC(2:0)
SC(2:0)
BCR
BCR
5
0
5
Channel B
66
Channel B
67
H
H
TOE
TOE
TOE
5-151
4
4
SSEL
SSEL
SSEL
3
3
0
0
0
Register Description (CCR0L)
Clock Mode Selection
Protocol Mode
2
2
0
0
0
CM(2:0)
CM(2:0)
CM(2:0)
1
1
SM(1:0)
SM(1:0)
SM(1:0)
PEB 20532
PEF 20532
2000-09-14
0
0