peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 229

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Register 85
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The Receive Status Byte ’RSTA’ contains comprehensive status information about the
last received frame (HDLC/PPP) or the last received ASYNC/BISYNC character.
The SCC attaches this status byte to the receive data and thus it should be read from
the RFIFO.
In HDLC/PPP modes the RSTA value can optionally be read from this register address;
in ASYNC and BISYNC modes a read to this register is not specified. In extended
transparent mode this status field does not apply.
Data Sheet
Bit
H
A
B
VFR
PE
PE
7
RSTA
Receive Status Byte
RDO
FE
6
0
read only
00
Channel A
58
written by SEROCCO-M to RFIFO;
read from RFIFO and evaluated by CPU
H
H
CRCOK
5
0
0
Channel B
A8
Receive Status Byte
H
RAB
4
0
0
229
3
0
0
HA(1:0)/
SU(1:0)
2
0
0
Register Description
C/R
1
0
0
PEB 20532
PEF 20532
2000-09-14
LA
P
P
0