tda19978bhv NXP Semiconductors, tda19978bhv Datasheet - Page 14

• Manufacturer Part Number: tda19978bhv
• Description: Quad Hdmi 1.3a Receiver Interface With Equalizer Hdtv Up To 1080p, Up To Uxga For Pc Formats
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA19978B_1
Product data sheet
8.18 4:2:2 formatter
8.19 Video port selection
8.20 Output buffers
8.21 VHREF timing generator
8.22 I
The 4:2:2 formatter contains the YCbCr 4:2:2 semi-planar and the YCbCr 4:2:2
ITU-R BT.656 formatting functions. The selection of these functions is made using the
I
The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be
included in the data stream based on the HREF, VREF and FREF positions from the
VHREF timing generator.
Specific codes programmed using the I
blanking period to mask gain and clamp calibration.
Each channel can be allocated to a specified video port using the I
“Output video port formats (mapping examples)” on page
the interface with video processing ICs. For example:
Each video port can be set to high-impedance using the I
The output buffers are LV-TTL compatible. The outputs can be switched between active
and high-impedance by the I
The outputs HREF, VREF and FREF can be set to high-impedance (Z) or forced LOW (L),
independently of the timing reference codes.
The VHREF timing generator outputs all of the timing signals used by the device:
The I
The slave address of the device is selected by pin A0.
2
2
C-bus.
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C-bus serial interface
In YCbCr 4:2:2 mode: the data frequency of the Y signal is equal to the pixel clock
frequency. While the data frequency of the Cb and Cr signals is equal to half the pixel
clock frequency
In semi-planar mode: the output clock frequency should be the same as the pixel
clock frequency
In ITU-R BT.656 mode: the data frequency should be the same as the formatter clock
frequency (e.g. pixel clock frequency
R, G or B in RGB 4:4:4 mode on pins VP[29:20]
Y, Cb or Cr in YUV 4:4:4 mode on pins VP[19:10]
Y or Cb-Cr in 4:2:2 semi-planar mode on pins VP[9:0]
Cb-Y-Cr-Y in 4:2:2 ITU-R BT.656 mode on pins VP[9:0]
VREF, HREF and FREF signals for SAV, EAV and active video area definition
VS and HS to change width and position compared with the HDMI inputs
2
C-bus serial interface enables the internal registers of the device to be programmed.
Rev. 01 — 7 August 2008
2
C-bus.
Quad HDMI 1.3a receiver with digital processing
2
C-bus can replace the data stream during the
2)
2
20) to optimize board layout at
C-bus.
TDA19978B
2
C-bus (see
© NXP B.V. 2008. All rights reserved.
Section 13
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