tda19978bhv NXP Semiconductors, tda19978bhv Datasheet - Page 2

• Manufacturer Part Number: tda19978bhv
• Description: Quad Hdmi 1.3a Receiver Interface With Equalizer Hdtv Up To 1080p, Up To Uxga For Pc Formats
• Manufacturer: NXP Semiconductors

NXP Semiconductors
2. Features
TDA19978B_1
Product data sheet
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Complies with the HDMI 1.3a, DVI 1.0 and CEA-861-D
Four (quad) independent HDMI inputs, up to the HDMI frequency of 235 MHz
Embedded auto-adaptive equalizer on all HDMI links
EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input
Supports color depth processing (8-bit, 10-bit or 12-bit per color)
Color gamut metadata packet with interrupt on each update, readable via the I
Up to four S/PDIF or I
with IEC 60958/IEC 61937 stream
HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I
HBR streams (e.g. DTS-HD master audio and Dolby TrueHD up to eight channels due
to HBR packet for stream with a frame rate up to 768 kHz) support
DSD and DST audio stream up to six DSD channels output for SACD with DST audio
packet support
Channel status decoder supports multi-channel reception
Improved audio clock generation using an external reference clock
System/master clock output (128/256/512
The HDMI interface supports:
Embedded oscillator (an external crystal can be used)
Frame and field detection for interlaced video signal
Sync timing measurements for format recognition
Improved system for measurements of blanking and video active area allowing an
accurate recognition of PC and TV formats
Repeater capability
Programmable color space input signal conversion from RGB-to-YCbCr or
YCbCr-to-RGB
Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the
ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656
8-bit, 10-bit or 12-bit output formats selectable using the I
in 4:4:4 format)
I
Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode
Internal video and audio pattern generator
Controllable using the I
DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s
LV-TTL outputs
Power-down mode
CMOS process
1.8 V and 3.3 V power supplies
Lead-free (Pb) HLQFP144 package
2
N
N
C-bus adjustable timing of video port (t
All HDTV formats up to 1920
60 Hz) with support for reduced blanking
PC formats up to UXGA (1600
Rev. 01 — 7 August 2008
2
S-bus outputs (eight channels) at a sampling rate up to 192 kHz
2
C-bus; 5 V tolerant and bit rate up to 400 kbit/s
Quad HDMI 1.3a receiver with digital processing
1080p at 50/60 Hz and WUXGA (1920
1200p at 60 Hz)
su(Q)
f
s
and t
) enables the use of the UDA1334BTS
h(Q)
)
2
C-bus (8-bit and 10-bit only
TDA19978B
© NXP B.V. 2008. All rights reserved.
2
S-bus outputs
1200p at
2
C-bus
2 of 36