at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet
at85c51snd3b
Available stocks
Related parts for at85c51snd3b
at85c51snd3b Summary of contents
Page 1
... Power-on Reset, Idle, Power-Down, Power-Off Modes – Software Programmable MCU Clock • Operating Conditions – Supply 1. for all Product range, plus 0.9V to 1.8V (3) ( MHz) MAX (4) (4) Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface AT85C51SND3B Preliminary 7632C–MP3–11/06 1 ...
Page 2
... The AT85C51SND3B includes Power Management with: 5V USB V 2.7V to 3.6V supply, 1.8V supply or alkaline battery supply (0.9V to 1.8V). External Nand Flash or Flash Card can be supplied by the AT85C51SND3B at 1.8V or 3V. The AT85C51SND3B supports many applications including: mobile phones, music play- ers, portable navigation, car audio, music in shopping centers, applications including MMC/SD Flash Cards in Industrial applications ...
Page 3
... Firmware to support – MP3 – WMA – ADPCM/WAV voice or line recording – JPEG Decoder Audio Codec – Internal DAC – FM inputs Memory Support – Nand-Flash – SD/MMC cards USB – High Speed, Full Speed – OTG (reduced Host) AT85C51SND3B 3 ...
Page 4
... Power Fail 3V Detector Regulator 1.8V 1.8V (1) DC-DC Regulator Debug Unit On Chip Debug Notes: 1. AT85C51SND3B2 only 2. AT85C51SND3B1 & AT85C51SND3B2 only AT85C51SND3B 4 Control Processor Unit Serial Peripheral Interface Enhanced X2 C51 Core Interrupt Controller Parallel Slave Interface Memory Unit Memory Controllers Configurable 64 Kbytes Code / Data RAM Nand Flash ...
Page 5
... Application Information The AT85C51SND3B derivatives allow design of 2 typical applications which differenti- ate by the power supply voltage: • • Figure 2. Typical Low Voltage 3V Application 7632C–MP3–11/06 The Very Low Voltage System The player operates at 1.8V and allows very low power consumption. ...
Page 6
... CVSS 14 P3.6/UVCON 15 P3.7/UID 16 ULVDD 17 DMF 18 DPF 19 UVSS 20 UHVDD 21 DPH 22 DMH 23 UVSS 24 UBIAS 25 Notes: 1. Leave these pins unconnected for AT85C51SND3B0 & AT85C51SND3B1 products 2. Leave these pins unconnected for AT85C51SND3B0 product AT85C51SND3B 6 AT85C51SND3B 75 NFD2 74 NFD3 73 NFD4 72 NFD5 71 NFD6 70 NFD7 69 P0.0/SD0/LD0 68 P0.1/SD1/LD1 67 P0.2/SD2/LD2 66 P0.3/SD3/LD3 65 P0 ...
Page 7
... Figure 4. AT85C51SND3B 100-pin BGA Package (no ADC DPH DMH UPDD B UBIAS UPVSS UVSS C NC AVSS1 RLVDD D MICIN LINR MICBIAS E AVREF LINL AVCM F NC APVSS APVDD X2 P4_2 H OCDR NC /DDAT J OCDT/ P5.1 P5.3 ISP K P5.0 P5.2 RST 7632C–MP3–11/ DPF DMF HVDD ...
Page 8
... Signals Description System Table 1. System Signal Description Table 2. Ports Signal Description AT85C51SND3B 8 Signal Name Type Description Reset Input Holding this pin low for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than V oscillator is running ...
Page 9
... IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. Timer 0 External Clock Input T0 I When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. AT85C51SND3B Alternate Function OCLK DCLK DDAT DSEL ...
Page 10
... Clock Controller Table 4. Clock Signal Description Table 5. Secure Digital Card / MutiMediaCard Controller Signal Description Memory Controllers SDDAT3:0 Table 6. Nand Flash / SmartMedia Card Controller Signal Description AT85C51SND3B 10 Signal Name Type Description Input of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to ...
Page 11
... USB High Speed Plus Data Upstream Port DMH I/O USB High Speed Minus Data Upstream Port USB VBUS Control line UVCON O UVCON is used to control the external VBUS power supply ON or OFF. Note: This output is requested for OTG mode. AT85C51SND3B Alternate Function - - - - P4.4 P4.5 P4.6 ...
Page 12
... Electret Microphone Bias Output Right Channel Output OUTR O Do not connect on AT85C51SND3B0 product Left Channel Output OUTL O Do not connect on AT85C51SND3B0 product Analog Common Mode Voltage AVCM I Connect this pin to external decoupling capacitor. Analog Reference Voltage AREF O Connect this pin to external decoupling capacitor. ...
Page 13
... SPI Slave Select Line SS I When in controlled slave mode, SS enables the slave mode. Signal Name Type Description Receive Serial Data RXD I/O RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. AT85C51SND3B Alternate Function - - Alternate Function P0.7:0 LD7:0 P5.0 LRD/LDE P5.3 LWR/LRW P5 ...
Page 14
... Table 13. Keypad Controller Signal Description MMI Interface Table 14. LCD Interface Signal Description LWR/LRW Power Management Table 15. Power Signal Description AT85C51SND3B 14 Signal Name Type Description Transmit Serial Data TXD O TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. ...
Page 15
... Connect this pin to LVDD or HVDD pin. Input/Output Circuit Ground IOVSS GND Connect this pin to VSS pin. Signal Name Type Description On Chip Debug Receive Input OCDR I OCDR receives data. On Chip Debug Transmit Output OCDT I/O OCDT transmits data. AT85C51SND3B Alternate Function - - - - - - - - Alternate Function - ISP 15 ...
Page 16
... Internal Pin Structure Table 17. Detailed Internal Pin Structure AT85C51SND3B 16 (1) Circuit IOVDD N IOVSS IOVDD IOVDD 2 osc periods Latch Output IOVSS HVDD HVDD 2 osc periods Latch Output IOVSS IOVDD IOVDD Pm Pw IOVSS IOVDD P N IOVSS Type Pins Input/Output RST IOVDD P0 ...
Page 17
... AT85C51SND3B (1) Circuit IOVDD P N IOVSS DPF DMF DPH DMH BVDD LVDD P N CVSS Type Pins SDCLK SCK NFCE3:0 NFCLE NFALE NFWE NFRE NFWP SMCE Output DSEL DDAT DCLK OCLK LWR/LE LA0/LRS LRD/LRW LCS UVCON TXD DPF Input/Output DMF ...
Page 18
... Notes: AT85C51SND3B 18 (1) Circuit - + AVSS AVSS - + 1. For information on resistor value, input/output levels, and drive capability, refer to Section “DC Characteristics”, page 242. 2. AT85C51SND3B2 only 3. AT85C51SND3B1 & AT85C51SND3B2 only Type Pins Output MICBIAS MICIN Input LINR LINL (2) OUTR Output (2) OUTL 7632C–MP3–11/06 ...
Page 19
... The Power Management of AT85C51SND3B dervatives implements all the internal power circuitry (regulators, links…) as well as power failure detector and reset circuitry. Power Supply The AT85C51SND3B2 embeds the regulators and step-up convertor to be able to operate from either USB power supply (5V nominal) or from a single cell battery such as AAA battery. ...
Page 20
... DC-DC shut-down is done by two different ways: • • Note: DC-DC Connection Figure 8 shows how to connect external components, inductance and components value along with power characteristics are specified in the section “DC characteristics”. Figure 8. Battery DC-DC Connection Note: AT85C51SND3B 20 HVDD C HV VSS Depending on power supply scheme, C LVDD DCEN ...
Page 21
... Power Reduction Mode Two power reduction modes are implemented in the AT85C51SND3B: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addi- tion to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode as detailed in Section “X2 Feature”, page 31 ...
Page 22
... Generate an enabled external interrupt. AT85C51SND3B 22 If IDL bit and PD bit are set simultaneously, the AT85C51SND3B enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. – Hardware clears IDL bit in PCON register which restores the clock to the CPU. ...
Page 23
... Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT85C51SND3B and vectors the CPU to address 0000h. 1. During the time that execution resumes, the internal RAM cannot be accessed; how- ever possible for the Port pins to be accessed ...
Page 24
... RST pin. A bad level leads to a wrong initialization of the internal registers like SFRs, Program Counter… and to unpredictable behavior of the microcontroller. A proper device reset initializes the AT85C51SND3B and vectors the CPU to address 0000h. RST input has a pull-up resistor allowing power-on reset by ...
Page 25
... IL and the oscillator are not stabilized. 2 parameters have to be taken DD V rise time, DD Oscillator startup time. IOVDD RST 1K + IOVSS IOVSS AT85C51SND3B + To CPU Core and Peripherals IOVSS From Internal Reset Source Power-on Reset , Other On-board ...
Page 26
... Registers Table 20. PCON Register PCON (0.87h) – Power Control Register Reset Value = 00011 0000b Table 21. PSTA Register PSTA (0.86h) – Power Status Register AT85C51SND3B VBCEN VBPEN DCPBST GF0 Bit Bit Number Mnemonic Description Battery Monitor Clock Enable Bit 7 VBCEN Set to enable the clock of the battery monitoring ...
Page 27
... Battery Monitor Error Flag 6 VBERR Set by hardware when conversion is out of min/max values. Reserved 5 - The value read from this bit is always 0. Do not set this bit. Battery Value 4-0 VB4:0 Refer to Table 18 for voltage value correspondence. AT85C51SND3B VB3 VB2 VB1 0 VB0 27 ...
Page 28
... Clock Controller The clock controller implemented in AT85C51SND3B derivatives is based on an on-chip oscillator feeding two on-chip Phase Lock Loop (PLL) dedicated for the USB controller (see Section “USB Controller”, page 85) and the Audio Controller (see Section “Audio Controller”, page 149). All internal clocks to the peripherals and CPU core are gener- ated by this controller ...
Page 29
... The reverse clock selection mechanism is implemented in order to support many oscillator frequencies and to minimize the PLL output jitter. 7632C–MP3–11/06 APVSS OSC 480 MHz PLL CLOCK CKGENE CKEN.7 PLLEN CKEN.6 Clock Generator Symbol AT85C51SND3B OSC PLL Clock 120 MHz 60 MHz PLOCK 48 MHz Clock CKEN ...
Page 30
... PLL is enabled. System clock generator block diagram is shown in Figure 19 and is based on a frequency selector controlled by SYSCKS1:0 bits in CKSEL (see Table 34) according to Table 26. The CPU clock can be disabled by entering the idle reduction mode as detailed in the Section “Power Management”, page 19. Note: AT85C51SND3B Divider PFLD Down PLLN3:0 PLLCLK ...
Page 31
... AT85C51SND3B needs only 6 clock periods per machine cycle. This feature called the “X2 feature” can be enabled using the X2 bit AT85C51SND3B to operate clock periods per machine cycle. As shown in Figure 19, both CPU and peripheral clocks are affected by this feature. Figure 20 shows the X2 mode switching waveforms ...
Page 32
... Table 28 Frequency division is done using MMCDIV4:0 bits in MMCCLK according to Table 29. Frequency configuration (selection and division) must be done prior to enable the MMC clock generation by setting MMCKEN bit in CKEN. Note: Figure 22. MMC Clock Generator Block Diagram and Symbol AT85C51SND3B 32 OSC 60 MHz 48 MHz 40 MHz ...
Page 33
... F 2 OSC MMCDIV4:0 Clock Division 00000 Disabled (no clock out) ÷ ≥ 00001 MMCDIV MMC S OSC CLOCK 120 MHz GEN SIOCKS CKSEL.2 SIOCKS Clock Selection ( OSC 1 120 MHz AT85C51SND3B ) CKEN.1 SIOCKEN SIO Clock 1 SIO CLOCK SIO Clock Symbol ) 33 ...
Page 34
... Registers Table 31. CKCON Register CKCON (0.8Fh) – Clock Control Register Reset Value = 0000 0000b AT85C51SND3B WDX2 OSCAMP OSCF1 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Watchdog Clock Control Bit ...
Page 35
... The value read from this bit is always 0. Do not set this bit. SIO Controller Clock Enable Bit 1 SIOCKEN Set to enable the SIO Clock. Clear to disable the SIO Clock. DF Controller / NF Controller Clock Enable Bit 0 DNFCKEN Set to enable the DFC/NFC Clock. Clear to disable the DFC/NFC Clock. AT85C51SND3B MMCKEN - SIOCKEN 0 DNFCKEN 35 ...
Page 36
... CKSEL (0.BAh) – Clock Selection Register Reset Value = 0000 0000b Table 34. PLLCLK Register PLLCLK (0.BCh) – PLL Clock Control Register Reset Value = 0000 0000b Table 35. MMCCLK Register MMCCLK (0.BDh) – MMC Clock Control Register MMCCKS2 Reset Value = 0000 0000b AT85C51SND3B DNFCKS2 DNFCKS1 DFCCKS0 PLLCKS1 ...
Page 37
... Special Function Registers SFR Pagination The AT85C51SND3B derivatives implement a SFR pagination mechanism which allows mapping of high number of peripherals in the SFR space. As shown in Figure 24, four pages are accessible through the PPCON (Peripheral Pagination Control) register (see Table 37). The four bits of PPCON: PPS0 to PPS3 are used to select one page as detailed in Table 36 ...
Page 38
... SFR Registers The Special Function Registers (SFRs) of the AT85C51SND3B fall into the categories detailed in Table 39 to Table 58. Address is identified as “P.XXh” where P can take the values detailed in Table 38 and XXh is the hexadecimal address from 80h to FFh Table 38. Page Address Notation The SFRs mapping within pages is provided together with SFR reset value in Table 58 to Table 58 ...
Page 39
... TR1 TF0 TR0 GATE1 C/T1# M11 M01 - - - - RA7 RA6 RA5 RA4 RA15 RA14 RA13 RA12 - - - - AT85C51SND3B ET1 EX1 ET0 EX0 ESPI EPSI EKB EUSB IPHT1 IPHX1 IPHT0 IPHX0 IPLT1 IPLX1 IPLT0 IPLX0 IPHSPI IPHPSI IPHKB IPHUSB IPLSPI IPLPSI ...
Page 40
... USB General Interrupt UDPADDH 1.E4h USB DPRAM Direct Access High UDPADDL 1.E5h USB DPRAM Direct Access Low OTGCON 1.E6h USB OTG Control OTGIEN 1.E7h USB OTG Interrupt Enable OTGINT 1.D1h USB OTG Interrupt AT85C51SND3B CBAX16:9 DBAX16:9 XBAX16:9 CSX7:0 ...
Page 41
... STALLRQ STALLRQC EPTYPE1 EPSIZE2:0 CFGOK OVERFI UNDERFI ZLPSEEN - - - - FIFOCON NAKINI RWAL NAKOUTI FLERRE NAKINE - NAKOUTE RXSTPE DAT7 BYCT7:0 - AT85C51SND3B RMWKUP DETACH EORSTI SOFI MSOFI SUSPI SOFE MSOFE SUSPE UADD6:0 - FNUM10:8 - MFNUM2:0 TSTK TSTJ SPDCONF - RESUME RESET SOFE RSMEDI RSTI ...
Page 42
... NFACT 1.A1h NF Action NFDAT 1.A2h NF Data NFDATF 1.A3h NF Data and Fetch Next NFSTA 1.98h NF Controller Status NFECC 1.A4h NF ECC 1 and 2 (FIFO 6 B) NFINT 1.A5h NF Interrupt NFIEN 1.A6h NF Interrupt Enable NFUDAT 1.A7h NF User Data AT85C51SND3B PFREEZE INMODE AUTOSW PTYPE1:0 PTOKEN1:0 ...
Page 43
... BPEN VSURND BBOOST ABACC APGPI3 APGPI2 APGPI1 APGPE3 APGPE2 APGPE1 APGPE0 - - - - - - Band - - - - - - - - - AT85C51SND3B BP15:8 BP7 CTPTR MBLOCK DFMT RFMT DATDIR DATEN RXCEN DBSIZE1:0 DATD1:0 BLEN7:0 DATFS CRC7S WFRS MD7:0 MC7:0 EOFI WFRI HFRI EOBI EOFM WFRM ...
Page 44
... Audio Codec Input Preamp Gain ADICON0 2.EEh Audio DAC Interface Control 0 ADICON1 2.EFh Audio DAC Interface Control 1 Note: Available in AT85C51SND3B1 & AT85C51SND3B2 only. Table 53. Audio Stream Codec SFRs Mnemonic Add Name ASCON 2.E1h Audio Stream Control ASSTA0 2.E2h Audio Stream Status 0 ASSTA1 2 ...
Page 45
... CDIV7:0 BDIV7:0 ADIV7 BUINV LCIFS ADSUH1 ADSUH0 SLW1:0 RSCMD LCYCW - - - - LD7:0 BUM7 KINL3:0 KPDE KDCPE KDCPL - AT85C51SND3B PEI FEI TI RI PEIE FEIE TIE RIE ACCW3 ACCW2 ACCW1 ACCW0 LCYCT LCEN LCRD LCRS - - - LCBUSY ...
Page 46
... TCON TMOD 88h 0000 0000 0000 0000 ( 80h 1111 1111 0000 0111 0/8 1/9 Notes: 1. SFR registers with least significant nibble address equal are bit-addressable. AT85C51SND3B 46 2/A 3/B 4/C SCHGPR2 SCHGPR1 SCHGPR0 0000 0000 0000 0000 0000 0000 MEMCBAX MEMDBAX MEMXBAX 0 0000 000 ...
Page 47
... XXXX XXXX 0000 0000 DFD0 DFD1 DFCRC 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT85C51SND3B 5/D 6/E 7/F RDFCAL RDFCAM RDFCAH 0000 0000 0000 0000 0000 0000 UDPADDL OTGCON OTGIEN 0000 0000 0000 0000 0000 0000 UDTST ...
Page 48
... P1 90h 1111 1111 88h ( 80h 1111 1111 0000 0111 0/8 1/9 Notes: 1. SFR registers with least significant nibble address equal are bit-addressable. 2. Available in AT85C51SND3B1 & AT85C51SND3B2 only. AT85C51SND3B 48 2/A 3/B 4/C SCHGPR2 SCHGPR1 SCHGPR0 0000 0000 0000 0000 0000 0000 APLDVOL APBDVOL APMDVOL ...
Page 49
... P0 SP 80h 1111 1111 0000 0111 0/8 1/9 Notes: 1. SFR registers with least significant nibble address equal are bit-addressable. 2. SVERS reset value depends on the silicon version 1111 1011 for AT85C51SND3B product. 7632C–MP3–11/06 2/A 3/B 4/C SCHGPR2 SCHGPR1 SCHGPR0 0000 0000 0000 0000 ...
Page 50
... Memory Space The AT85C51SND3B derivatives implement an “all in one” 64K bytes of RAM split between the three standard C51 memory segments: • • • To satisfy application needs in term of CODE and XDATA sizes, size and base address of XDATA and CODE segments and base address of DATA segment can be dynami- cally configured ...
Page 51
... MEMDBAX (see Table 66) for the data segment base address. MEMXBAX (see Table 67) for the xdata segment base address. MEMCSX (see Table 68) for the code segment size. MEMXSX (see Table 69) for the code segment size. AT85C51SND3B 7Fh 2Fh Bit-Addressable Space (Bit Addresses 0-7Fh) ...
Page 52
... In this figure italicized address are the logical address within segments. Figure 27. Memory Segment Configuration Registers Table 64. PSW Register PSW (S:8Eh) – Program Status Word Register Reset Value = 0000 0000b AT85C51SND3B 52 FFh FFFFh 256-byte DATA FF00h 00h ...
Page 53
... Bit Bit Number Mnemonic Description XDATA Base Address Most Significant Bits of Context MEMPID 7-0 XBAX16:9 17-bit CODE Base Address: X XXXX XXX0 0000 0000b. 512-byte alignment, no offset CSX7 CSX6 CSX5 CSX4 AT85C51SND3B CBAX12 CBAX11 CBAX10 DBAX12 DBAX11 DBAX10 4 ...
Page 54
... Reset Value MEMCSX = 1110 1111b Table 69. MEMXSX Register MEMXSX (0.F6h) – Memory Management XDATA Size Register Reset Value MEMXSX = 0000 1110b AT85C51SND3B 54 Bit Bit Number Mnemonic Description CODE Size Bits of Context MEMPID 7-0 CSX7:0 Size is equals to (CSX+1) x 256 bytes. CODE sizes available: from 256 bytes to 64 Kbytes, by 256-byte steps. ...
Page 55
... When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal AT85C51SND3B activity (e.g., timer overflow the initiation of electrical signals external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is programmed by the system designer, who determines priority of interrupt service relative to normal code execution and other interrupt service routines ...
Page 56
... Interrupt Name INT0 Timer 0 INT1 Timer 1 Serial I/O Port Data Flow Controller Audio Processor USB Controller Keyboard Parallel Slave Interface Serial Peripheral Interface Nand Flash Controller MMC Controller Reserved Reserved AT85C51SND3B 56 Interrupt Address Priority Number Vectors 0 (Highest Priority) C:0003h 1 C:000Bh 2 C:0013h 3 C:001Bh 4 C:0023h 5 ...
Page 57
... IEN0.6 USB Controller EUSB IEN1.0 Keyboard EKB IEN1.1 PSI Interface EPSI IEN1.2 SPI Interface ESPI IEN1.3 NF Controller ENFC IEN1.4 MMC Controller EMMC EA IEN1.5 IEN0.7 Interrupt Enable AT85C51SND3B Highest Priority 00 Interrupts ...
Page 58
... Minimum Pulse Timings). A level-triggered interrupt pin held low or high for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode) guarantees detection. Edge-triggered external interrupts must hold the request pin low for at least 6 peripheral clock periods. Figure 30. Minimum Pulse Timings AT85C51SND3B 58 INT0 IT0/1 TCON ...
Page 59
... Set to enable external interrupt 1. Clear to disable external interrupt 1. T0 Overflow Interrupt Enable Bit 1 ET0 Set to enable timer 0 overflow interrupt. Clear to disable timer 0 overflow interrupt. EX0 Interrupt Enable Bit 0 EX0 Set to enable external interrupt 0. Clear to disable external interrupt 0. AT85C51SND3B ET1 EX1 ET0 0 EX0 59 ...
Page 60
... Table 73. IEN1 Register IEN1 (0.B1h) – Interrupt Enable Register 1 Reset Value = 0000 0000b AT85C51SND3B EMMC ENFC Bit Bit Number Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these bits. MMC/SD Interrupt Enable Bit 5 EMMC Set to enable MMC/SD interrupt ...
Page 61
... EX1 Interrupt Priority Level Msb 2 IPHX1 Refer to Table 70 for priority level description. T0 Interrupt Priority Level Msb 1 IPHT0 Refer to Table 70 for priority level description. EX0 Interrupt Priority Level Msb 0 IPHX0 Refer to Table 70 for priority level description. AT85C51SND3B IPHT1 IPHX1 IPHT0 0 IPHX0 61 ...
Page 62
... Table 75. IPH1 Register IPH1 (0.B3h) – Interrupt Priority High Register 1 Reset Value = 0000 0000b AT85C51SND3B IPHMMC IPHNFC Bit Bit Number Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these bits. MMC/SD Interrupt Priority Level Msb ...
Page 63
... EX1 Interrupt Priority Level Lsb 2 IPLX1 Refer to Table 70 for priority level description. T0 Interrupt Priority Level Lsb 1 IPLT0 Refer to Table 70 for priority level description. EX0 Interrupt Priority Level Lsb 0 IPLX0 Refer to Table 70 for priority level description. AT85C51SND3B IPLT1 IPLX1 IPLT0 0 IPLX0 63 ...
Page 64
... Table 77. IPL1 Register IPL1 (0.B2h) – Interrupt Priority Low Register 1 Reset Value = 0000 0000b AT85C51SND3B IPLMMC IPLNFC Bit Bit Number Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these bits. MMC/SD Interrupt Priority Level Lsb ...
Page 65
... Timers/Counters The AT85C51SND3B derivatives implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request ...
Page 66
... Mode 0 configures Timer 13-bit Timer which is set 8-bit Timer (TH0 reg- ister) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 32). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 33 gives the overflow period calculation formula. AT85C51SND3B 66 PER 0 Timer 0 ...
Page 67
... TCON Reg = TFx PER TIMx ÷ C/Tx# TMOD Reg GATEx TMOD Reg TRx TCON Reg = TFx PER AT85C51SND3B THx TLx Overflow TFx (8 bits) (5 bits) TCON Reg 6 ⋅ (16384 – (THx, TLx)) F TIMx THx TLx Overflow TFx (8 bits) (8 bits) TCON Reg ⋅ ...
Page 68
... Thus, operation of Timer 1 is restricted when Timer mode 3. Figure 39 gives the auto-reload period calculation formulas for both TF0 and TF1 flags. Figure 38. Timer/Counter 0 in Mode 3: 2 8-bit Counters CLOCK INTx CLOCK Figure 39. Mode 3 Overflow Period Formula AT85C51SND3B 68 TIMx ÷ C/Tx# ...
Page 69
... When Timer mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. AT85C51SND3B Timer 0 Interrupt TF0 Request TCON ...
Page 70
... Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 41. Timer Interrupt System AT85C51SND3B important to stop the Timer/Counter before changing modes. M11 ...
Page 71
... Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0 pin. Interrupt 0 Type Control Bit 0 IT0 Clear to select low level active (level triggered) for external interrupt 0 (INT0). Set to select falling edge active (edge triggered) for external interrupt 0. AT85C51SND3B IE1 IT1 ...
Page 72
... Table 82. TMOD Register TMOD (0.89h) – Timer/Counter Mode Control Register Reset Value = 0000 0000b Table 83. TH0 Register TH0 (0.8Ch) – Timer 0 High Byte Register Reset Value = 0000 0000b AT85C51SND3B GATE1 C/T1# M11 M01 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit ...
Page 73
... Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer Bit Bit Number Mnemonic Description 7-0 High Byte of Timer Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 1 AT85C51SND3B ...
Page 74
... Table 87. SCHCLK Register SCHCLK (0.FEh) – Scheduler Clocks Register Reset Value = 0000 0000b AT85C51SND3B T0ETB2 T0ETB1 T0ETB0 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Timer 0 Enhanced Time Base Bits ...
Page 75
... Watchdog Timer The AT85C51SND3B derivatives implement a hardware Watchdog Timer (WDT) that automatically resets the chip allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 42, the 14-bit prescaler is fed by the WDT clock detailed in Section “ ...
Page 76
... INT0, INT1 or keyboard interrupt. To ensure that the WDT does not overflow shortly after exiting the Power-down mode recommended to clear the WDT just before entering Power-down mode. The WDT is cleared and disabled if the Power-down mode is terminated by a reset. AT85C51SND3B 76 = WDT ...
Page 77
... Watchdog Control Value Bit Bit Number Mnemonic Description Reserved 7-3 - The value read from these bits is indeterminate. Do not set these bits. Watchdog Timer Time-Out Selection Bits 2-0 WTO2:0 Refer to Table 88 for time-out periods. AT85C51SND3B WTO2 WTO1 WTO0 ...
Page 78
... Data Flow Controller The Data Flow Controller (DFC) implemented in the AT85C51SND3B derivatives is the multimedia data transfer manager two data transfers can be established through two physical data channels between a source peripheral and a destination peripheral. Figure 45 shows which peripherals are connected to the internal bus which are: the CPU internal bus, the multimedia data bus and the DFC control bus ...
Page 79
... DFCRC register. (2) 1. This double write or read sequence can be reset by clearing the CRCEN bit. 2. The CRC value is not reset at start- new data transfer. AT85C51SND3B DPS . DPS takes value from 0 (1-byte data packets. , CRC is available to user by reading two bytes ...
Page 80
... In case a data flow transfer is aborted, the remaining number of data packets to be transmitted can be retrieved by reading two bytes with MSB first from the data flow descriptor register DFD0 (channel DFD1 (channel 1). This feature is of interest in case of logical data flow management over a physical channel. Note: AT85C51SND3B 80 DFPRIO1 DFPRIO0 Assignment Description ...
Page 81
... An abort command never sets flags while in the process of writing DFD. EOFI0 DFCSTA.1 EOFE0 DFCCON.2 EOFI1 DFCSTA.5 EOFE1 DFCCON.6 AT85C51SND3B DFC Interrupt Request EDFC IENx.y 81 ...
Page 82
... Registers Table 94. DFCON Register DFCON (1.89h) – DFC Control Register Reset Value = 0000 0000b Table 95. DFCSTA Register DFCSTA (1.88h Bit Addressable) – DFC Channel Status Register AT85C51SND3B DFRES - DFCRCEN Bit Bit Number Mnemonic Description Reserved 5 - The value read from this bit is always 0. Do not set this bit. ...
Page 83
... Set to acknowledge the channel 0 EOF interrupt (clear EOFI0 flag). 1 EOFIA0 Clearing this bit has no effect. The value read from this bit is always 0. Reserved 0 - The value read from this bit is always 0. Do not set this bit. AT85C51SND3B DFABT0 EOFE0 EOFIA0 ...
Page 84
... DFD0 (1.8Ah) – DFC Channel 0 Data Flow Descriptor Register Reset Value = 0000 0000b Table 98. DFD1 Register DFD1 (1.8Bh) – DFC Channel 1 Data Flow Descriptor Register Reset Value = 0000 0000b Table 99. DFCRC Register DFCRC (1.8Ch) – DFC CRC Data Register Reset Value = 0000 0000b AT85C51SND3B DFD0D7 DFD0D6 DFD0D5 ...
Page 85
... Figure 49. USB Controller Block Diagram USB Connection Figure 50 shows the connection of the AT85C51SND3B to the USB connector and the the connection of the RC filter to the UBIAS pin. DPF and DMF pins are connected through 2 termination resistors. Value of all discrete components is detailed in the Section “DC Characteristics”, page 242. 7632C– ...
Page 86
... This is also true for the Host mode. Figure 51 shows the USB controller main states after power-on. Power-On and Reset Figure 51. USB Controller Reset State Machine USB Controller state after an hardware reset is ‘Reset’. In this state: • • • • • AT85C51SND3B 86 UBIAS ON Out OTG 5V ...
Page 87
... USBCON.1 VBUSTI USBINT.0 VBUSTE USBCON.0 STOI OTGINT.5 STOE OTGIEN.5 HNPERRI OTGINT.4 HNPERRE OTGIEN.4 ROLEEXI OTGINT.3 ROLEEXE OTGIEN.3 BCERRI OTGINT.2 BCERRE OTGIEN.2 VBERRI OTGINT.1 VBERRE OTGIEN.1 SRPI OTGINT.0 SRPE OTGIEN.0 AT85C51SND3B USB Controller Interrupt Request EUSB IEN1.0 USB General & OTG Interrupt 87 ...
Page 88
... Moreover, when FRZCLK is set, only the following interrupts may be triggered: • • • AT85C51SND3B 88 IDTI: ID Pad detection (insert, remove) VBUSTI: VBUS plug-in detection (insert, remove) SRPI: SRP detected ROLEEXI: Role Exchanged VBERRI: Drop on VBUS Detected BCERRI: Error during the B-Connection ...
Page 89
... Full-Speed only mode (Full-Speed pad) 01 Shall be done before setting USBE. High-Speed only mode (High-Speed pad) 10 Shall be used in debug mode. 11 Full-Speed only mode (High-Speed pad) XX Use Full-Speed pad USBE bit must be cleared. DPACC bit and the base address DPADD10:0 must be set. AT85C51SND3B 89 ...
Page 90
... ALLOC. Then, the “k “slides” down. Note that the “k The following figure illustrates the allocation and reorganization of the USB memory in a typical example: Figure 54. Allocation and reorganization USB memory flow AT85C51SND3B 90 Unused Endpoint Endpoint 0 USB DPRAM ...
Page 91
... In the “active” mode, the pad is working. Idle mode USBE=0 | DETACH=1 | suspend Suspend detected pad => Idle state SUSPI WAKEUPI Pad Status Active AT85C51SND3B USBE=1 & DETACH=0 & suspend Active mode Clear Suspend by software Resume detected pad => Active state Clear Resume by software Idle Active ...
Page 92
... Table 101. OTG Timer Configuration Plug-in detection The USB connection is detected by the VBUS pad, thanks to the following architecture: Figure 57. Plug-in Detection Input Block Diagram AT85C51SND3B 92 AWaitVrise time-out. [OTG] chapter 6.6.5.1 VbBusPulsing. [OTG] chapter 5.3.4 PdTmOutCnt. [OTG] chapter 5.3.2 SRPDetTmOut. [OTG] chapter 5.3.3 PAGE1:0 ...
Page 93
... VBUS is set when the voltage on the UVCC pin is higher or equal to 4.4 V. VBUS is cleared when the voltage on the UVCC pin is lower than 1.4 V. VBUS is set when the voltage on the UVCC pin is higher or equal to 1.4 V. VBUS is cleared when the voltage on the UVCC pin is lower than 1.4 V. AT85C51SND3B 93 ...
Page 94
... The IDTI interrupt is triggered when a A-plug (Host) is plugged or unplugged. The inter- rupt is not triggered when a B-plug (Peripheral) is plugged or unplugged. The IDTI interrupt may be triggered even if the USB controller is disabled. Registers USB general registers Table 102. USBCON Register USBCON (1.E1h) – USB General Control Register AT85C51SND3B 94 VDD Internal Pull Up UID USBSTA.1 7 ...
Page 95
... Set by hardware when a transition (high to low, low to high) has been detected 1 IDTI on the UID pin. Shall be cleared by software. VBUS Transition Interrupt Flag Set by hardware when a transition (high to low, low to high) has been detected 0 VBUSTI on the UVCC pin. Shall be cleared by software. AT85C51SND3B SPEED ...
Page 96
... UDPADDH (1.E4h) – USB Dual Port Ram Direct Access High Register Reset Value = 0000 0000b Table 106. UDPADDL Register UDPADDL (1.E5h) – USB Dual Port Ram Direct Access High Register Reset Value = 0000 0000b Table 107. OTGCON Register OTGCON (1.E6h) – USB OTG Control Register AT85C51SND3B DPACC - ...
Page 97
... See Section “OTG Timers Customizing” for more details. Reserved 4-3 - The value read from these bits is always 0. Do not set these bits. Value Bit 2-0 VALUE2:0 Set to initialize the new value of the timer. See Section “OTG Timers Customizing” for more details. AT85C51SND3B VALUE2 ...
Page 98
... Table 109. OTGIEN Register OTGIEN (1.E7h) – USB OTG Interrupt Enable Register Reset Value = 0000 0000b Table 110. OTGINT Register OTGINT (1.D1h) – USB Global Interrupt Register AT85C51SND3B STOE HNPERRE Bit Bit Number Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these bits. ...
Page 99
... Set by hardware when an error occur during the B-Connection. Shall be cleared by software. V-Bus Error Interrupt Flag 1 VBERRI Set by hardware when a drop on VBus has been detected. Shall be cleared by software. SRP Interrupt Flag Set by hardware when a SRP has been detected. Shall be used in the Host 0 SRPI mode only. Shall be cleared by software. AT85C51SND3B 99 ...
Page 100
... Resuming the USB interface • • • • AT85C51SND3B 100 Power-On USB pads regulator Wait USB pads regulator ready state Configure PLL interface Enable PLL Check PLL lock Enable USB interface Configure USB interface (USB speed, Endpoints configuration...) ...
Page 101
... USB device controller internal state is reset (all the registers are reset to their default value. Note that DETACH is set.) the endpoint banks are reset the pull up are not activated (mode Detach) a classic reset (Full-speed High-speed reset (High-speed). AT85C51SND3B <any other state> USBE=0 Idle ...
Page 102
... These two registers permits to easily switch from an endpoint under DFC data transfer to the default control endpoint when a SETUP is received, without reprogramming the EPNUM register: AT85C51SND3B 102 the internal state machine on that endpoint, the Rx and Tx banks are cleared and their internal pointers are restored, the UEINTX, UESTA0X and UESTA1X are restored to their reset value ...
Page 103
... ERROR The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept) It resets the data toggle field. The DPRAM memory associated to the endpoint is still reserved. the USB device, after power-up, responds at address 0 AT85C51SND3B Select the endpoint Activate the endpoint Configure: - the endpoint direction ...
Page 104
... Detach The reset value of the DETACH bit possible to re-enumerate a device, simply by setting and clearing the DETACH bit. • AT85C51SND3B 104 the host sends a SETUP command (SET_ADDRESS(addr)), the firmware records that address in UADD, but keep ADDEN cleared, the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet), then, the firmware can enable the USB device address by setting ADDEN ...
Page 105
... RMWKUP is cleared by hardware at the end of the “upstream resume”. If the controller detects a good “End Of Resume” signal from the host, an EORSMI interrupt is triggered (if enabled). – STALLRQ (enable stall request) – STALLRQC (disable stall request) – STALLI (stall sent interrupt) AT85C51SND3B UVREF Detach, then Attach EN 105 ...
Page 106
... SETUP RXSTPI HW RXOUTI TXINI AT85C51SND3B 106 RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to acknowledge the packet and to clear the endpoint bank. RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to acknowledge the packet and to clear the endpoint bank. ...
Page 107
... CON bit in order to free the current bank. If the OUT Endpoint is composed of multiple 7632C–MP3–11/06 DATA set transmit ready wait (transmit complete OR Receive complete) if receive complete, clear flag and return if transmit complete, continue AT85C51SND3B STATUS OUT OUT NAK HW SW 107 ...
Page 108
... The acknowledge of the RXOUTI interrupt is always performed by software. Detailed Description standard Mode Without In this mode (AUTOSW cleared), the data are read by the CPU, following the next flow: AUTOSW • • • AT85C51SND3B 108 NAK OUT SW read data from CPU SW BANK 0 DATA ...
Page 109
... End Of Transfer from the DFC. programming of the DFC, EPINTx (RXOUTE set, RXOUTI set) or polling on RXOUTI=1 or FIFOCON=1, The CPU acknowledges the interrupt by clearing RXOUTI, poll the wait of the transfer: (while RWAL is set: wait), Clear FIFOCON which frees the bank and switch to the next one. AT85C51SND3B 109 ...
Page 110
... Detailed Description Standard Mode without In this mode (AUTOSW cleared), the data are written by the CPU, following the next AUTOSW flow: • • • AT85C51SND3B 110 DATA IN ACK (bank DATA ...
Page 111
... RWAL is set: wait), Clear FIFOCON which frees the bank and switch to the next one control transaction: ZLP data OUT received during a IN stage isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN stage on the IN endpoint … AT85C51SND3B 111 ...
Page 112
... RXOUTI interrupt is also triggered (if enabled). The bank is filled with the first bytes of the packet not possible to have overflow error during IN stage, in the CPU side, since the CPU should write only if the bank is ready to access data (TXINI=1 or RWAL=1). AT85C51SND3B 112 Endpoint Abort Clear UEIENX ...
Page 113
... WAKEUPI: Wake up EORSTI: end of reset (Speed Initialization) SOFI: start of frame (FNCERR= 0) MSOFI: micro start of frame (FNCERR= 0) SUSPI: suspend detected after inactivity SOFI: CRC error in frame number of SOF (FNCERR= 1) MSOFI: CRC error in frame number of micro-SOF (FNCERR= 1) AT85C51SND3B USB Device Interrupt 113 ...
Page 114
... Processing interrupts are generated when the following events are triggered: • • • Exception Interrupts are generated when the following events are triggered: • • • • • • AT85C51SND3B 114 OVERFI UESTA0X.6 UNDERFI UESTA0X.5 FLERRE UEIENX.7 NAKINI UEINTX.6 NAKINE UEIENX.6 NAKOUTI UEINTX ...
Page 115
... This triggers an interrupt if 4 WAKEUPI WAKEUPE is set. Shall be cleared by software (USB clock inputs must be enabled before). Setting by software has no effect. See Section “Suspend, Wake-Up and Resume” for more details. AT85C51SND3B ...
Page 116
... Reset Value = 0000 0000b Table 114. UDIEN Register UDIEN (1.DAh) – USB Device Global Interrupt Enable Register AT85C51SND3B 116 Bit Bit Number Mnemonic Description End Of Reset Interrupt Flag Set by hardware when an “End Of Reset” has been detected by the USB 3 EORSTI controller. This triggers an USB interrupt if EORSTE is set. ...
Page 117
... Frame Number Upper Flag Set by hardware. These bits are the 3 MSB of the 11-bits Frame Number 2-0 FNUM10:8 information. They are provided in the last received SOF packet. FNUM is updated if a corrupted SOF is received FNUM7 FNUM6 FNUM5 FNUM4 AT85C51SND3B UADD3 UADD2 UADD1 ...
Page 118
... UDMFN (1.DEh) – USB Device Frame Number Register Reset Value = 0000 0000b USB Device Endpoint Registers Table 119. UENUM Register UENUM (1.C9h) – USB Endpoint Number Selection Register Reset Value = 0000 0000b AT85C51SND3B 118 Bit Bit Number Mnemonic Description Frame Number Lower Flag ...
Page 119
... Clearing by software has no effect. Endpoint Number Select Bit 2 EPNUMS Set to configure the EPNUM used by the DFC. Clear to select the EPNUM used by the CPU. DFC Ready Bit 1 DFCRDY Set to resume/enable the DFC interface. Clear to pause the DFC interface. AT85C51SND3B EPRST3 EPRST2 EPRST1 ...
Page 120
... Reset Value = 0000 0000b Table 122. UECFG0X Register UECFG0X (1.CCh) – USB Endpoint Configuration 0 Register Reset Value = 0000 0000b Table 123. UECFG1X Register UECFG1X (1.CDh) – USB Endpoint Configuration 1 Register AT85C51SND3B 120 Bit Bit Number Mnemonic Description Endpoint Enable Bit Set to enable the endpoint according to the device configuration. Endpoint 0 shall ...
Page 121
... Zero Length Packet Seen (bit / Flag) 4 ZLPSEEN Set by hardware, as soon as a ZLP has been filtered during a transfer. Shall be cleared by the software. Setting by software has no effect. AT85C51SND3B 100b: 128 bytes 101b: 256 bytes 110b: 512 bytes 111b: Reserved. Do not use this configuration. ...
Page 122
... Reset Value = 0000 0000b Table 125. UESTA1X Register UESTA1X (1.CFh) – USB Endpoint Status 1 Register Reset Value = 0000 0000b AT85C51SND3B 122 Bit Bit Number Mnemonic Description Data Toggle Sequencing Flag Set by hardware to indicate the PID data of the current bank: 00b: Data0 ...
Page 123
... Shall be cleared by software to acknowledge the interrupt. Setting by software RXOUTI / has no effect. 2 KILLBK Kill Bank IN Bit Set this bit to kill the last written bank. Cleared by hardware when the bank is killed. Clearing by software has no effect. See Section “Abort” for more details on the Abort. AT85C51SND3B RXSTPI RXOUTI STALLI 0 ...
Page 124
... Reset Value = 0000 0000b Table 127. UEIENX Register UEIENX (1.D2h) – USB Endpoint Interrupt Enable Register Reset Value = 0000 0000b AT85C51SND3B 124 Bit Bit Number Mnemonic Description Stall Interrupt Flag Set by hardware to signal that a STALL handshake has been sent, or that a CRC ...
Page 125
... Set by the hardware. BYCT10:0 is: - (for IN endpoint) increased after each writing into the endpoint and 7-0 BYCT7:0 decremented after each byte sent, - (for OUT endpoint) increased after each byte sent by the host, and decremented after each byte read by the software. AT85C51SND3B DAT3 DAT2 ...
Page 126
... Table 131. UEINT Register UEINT (1.D6h) – USB Endpoint Interrupt Register Reset Value = 0000 0000b. AT85C51SND3B 126 EPINT6 EPINT5 EPINT4 Bit Bit Number Mnemonic Description Reserved 7 - The value read from these bits is always 0. Do not set these bits. Endpoint Interrupts Bits ...
Page 127
... The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to enter in ‘Host Ready’ state. 7632C–MP3–11/06 Device Clock stopped disconnection Macro off Host Idle Device connection Device disconnection Host Ready SOFE=0 Host SOFE=1 Suspend AT85C51SND3B <any other state> 127 ...
Page 128
... These two registers permits to easily switch from a Pipe under DFC data transfer to the default control Pipe when a SETUP has to be sent, without reprogramming the EPNUM register: AT85C51SND3B 128 Clearing PNUMS. Setting PNUM with the Pipe number which will be managed by the CPU. ...
Page 129
... The firmware has to configure the Default Control Pipe with the following parameters: Type: Control Token: SETUP Data bank: 1 Size: 64 Bytes AT85C51SND3B Enable the pipe Select the Pipe type: * Type (Control, Bulk, Interrupt) * Token (IN, OUT , SET UP) * Endpoint number Configure the Pipe memory: ...
Page 130
... In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM register and performs read or write action on the UPDATX register. Control Pipe A Control transaction is composed of 3 phases: Management • • • AT85C51SND3B 130 Host Ready SOFE=1 or HWUP=1 SETUP Data (IN or OUT) ...
Page 131
... Note: if the firmware decides to switch to suspend mode (clear SOFE) even if a bank is ready to be sent, the USB controller will automatically exit from Suspend mode and the bank will be sent. 7632C–MP3–11/06 SETUP: Data0 OUT: Data1 IN: Data1 (expected data toggle) AT85C51SND3B 131 ...
Page 132
... FIFOCON write data from CPU Example with 2 OUT data banks TXOUT SW FIFOCON write data from CPU Example with 2 OUT data banks TXOUT SW FIFOCON write data from CPU AT85C51SND3B 132 DATA OUT (bank 0) SW BANK 0 DATA OUT (bank write data from CPU ...
Page 133
... INMODE = 1. The USB controller will perform infinite IN request until the firmware freezes the Pipe read data from CPU BANK 0 DATA IN ACK (to bank read data from CPU BANK 0 AT85C51SND3B DATA ACK (to bank read data from CPU BANK 0 SW read data from CPU BANK 1 133 ...
Page 134
... In this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI interrupt from being triggered. Interrupt Figure 67 shows all the host interrupts sources while Figure 68 details the pipe interrupt sources. Figure 67. USB Host Controller Interrupt System AT85C51SND3B 134 HWUPI UHINT.6 HWUPE UHIEN.6 HSOFI UHINT ...
Page 135
... OVERFI UPSTAX.6 UNDERFI UEPSTAX.5 FLERRE UPIENX.7 NAKEDI UPINTX.6 NAKEDE UPIENX.6 PERRI UPINTX.4 PERRE UPIENX.4 TXSTPI UPINTX.3 TXSTPE UPIENX.3 TXOUTI UPINTX.2 TXOUTE UPIENX.2 RXSTALLI UPINTX.1 RXSTALLE UPIENX.1 RXINI UPINTX.0 RXINE UPIENX.0 AT85C51SND3B Pipe n (n= 0-6) Pipes PINTn Interrupt UPINT.n 135 ...
Page 136
... Registers General USB Host Registers Table 132. UHCON Register UHCON (1.D9h) – USB Host General Control Register Reset Value = 0000 0000b Table 133. UHINT Register UHINT (1.D8h) – USB Host General Interrupt Register AT85C51SND3B 136 Bit Bit Number Mnemonic Description ...
Page 137
... RSTE Set this bit to enable the RSTI interrupt. Clear this bit to disable the RSTI interrupt. Device Disconnection Interrupt Enable 1 DDISCE Set this bit to enable the DDISCI interrupt. Clear this bit to disable the DDISCI interrupt. AT85C51SND3B RSMEDE RSTE DDISCE 0 DCONNE ...
Page 138
... Table 135. UHADDR Register UHADDR (1.DBh) – USB Host Address Register Reset Value = 0000 0000b Table 136. UHFNUMH Register UHFNUMH (1.DCh) – USB Host Frame Number High Register Reset Value = 0000 0000b AT85C51SND3B 138 Bit Bit Number Mnemonic Description Device Connection Interrupt Enable ...
Page 139
... The value read from these bits is always 0. Do not set these bits. Pipe Number Select the pipe using this register. The USB Host registers ended 2-0 PNUM2:0 correspond then to this number. This number is used for the USB controller following the value of the PNUMD bit. AT85C51SND3B FNUM3 FNUM2 ...
Page 140
... Table 140. UPRST Register UPRST (1.CAh) – USB Host Pipe Reset Register Reset Value = 0000 0000b Table 141. UPCONX Register UPCONX (1.CBh) – USB Host Pipe Control Register AT85C51SND3B 140 P6RST P5RST P4RST Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. ...
Page 141
... Select the Token to associate to the Pipe: - 00: SETUP 5-4 PTOKEN1 10: OUT - 11: reserved Pipe Endpoint Number 3-0 PEPNUM3:0 Set this field according to the Pipe configuration. Set the number of the Endpoint targeted by the Pipe. This value is from 0 and 15. AT85C51SND3B PEPNUM3 PEPNUM2 PEPNUM1 0 PEPNUM0 141 ...
Page 142
... Table 143. UPCFG1X Register UPCFG1X (1.CDh) – USB Pipe Configuration 1 Register Reset Value = 0000 0000b Table 144. UPCFG2X Register UPCFG2X (1.CFh) – USB Pipe Configuration 2 Register Reset Value = 0000 0000b AT85C51SND3B 142 PSIZE2 PSIZE1 PSIZE0 Bit Bit Number Mnemonic Description ...
Page 143
... For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer. NBUSYBK1: For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from 1-0 0 the Device. 00bAll banks are free 01b1 busy bank 10b2 busy banks 11bReserved. AT85C51SND3B DTSEQ1 DTSEQ0 NBUSYBK1 NBUSYBK0 0 143 ...
Page 144
... Table 146. UPINRQX Register UPINRQX (1.DFh) – USB Pipe IN Number Of Request Register Reset Value = 0000 0000b Table 147. UPERRX Register UPERRX (1.D7h) – USB Pipe Error Register Reset Value = 0000 0000b AT85C51SND3B 144 INRQ7 INRQ6 INRQ5 INRQ4 Bit Bit Number ...
Page 145
... Shall be cleared to handshake the interrupt. Setting by software has no effect. 1 CRCERR For Isochronous Pipe: Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if the TXSTPE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. AT85C51SND3B TXSTPI TXOUTI ...
Page 146
... Reset Value = 0000 0000b Table 149. UPIENX Register UPIENX (1.D2h) – USB Pipe Interrupt Enable Register Reset Value = 0000 0000b Table 150. UPDATX Register UPDATX (1.D3h) – USB Pipe Data Register AT85C51SND3B 146 Bit Bit Number Mnemonic Description IN Data received Set by hardware when a new USB message is stored in the current bank of the ...
Page 147
... Set by the hardware. PBYCT10:0 is: - (for OUT Pipe) increased after each writing into the Pipe and decremented after 7-0 PBYCT7:0 each byte sent, - (for IN Pipe) increased after each byte received by the host, and decremented after each byte read by the software. AT85C51SND3B ...
Page 148
... Table 153. UPINT Register UPINT (1.D6h) – USB Pipe IN Number Of Request Register Reset Value = 0000 0000b AT85C51SND3B 148 PINT6 PINT5 PINT4 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Pipe Interrupts Bits ...
Page 149
... Audio Controller The Audio Controller implemented in AT85C51SND3B derivatives is based on four func- tional blocks detailed in the following sections: • • • • Figure 69. Audio Controller Block Diagram Clock Generator The clock generator generates the audio controller clocks based on the audio clock issued by the clock controller as detailed in Section “System Clock Generator”, page 30. ...
Page 150
... APRDYI is cleared when the buffer becomes empty. These flags can generate an interrupt when APREQE bit and APRDYE bit in APIEN are respectively set (see Section “Interrupts”). AT85C51SND3B 150 Audio Buffer CPU/DFC ...
Page 151
... Clearing DAPEN bit resets the code writing pointer address to 0000h. 2. Toggling APLOAD bit leaves the code writing pointer address unchanged. Digital volume control 3-bands equalizer Bass boost effect Virtual surround effect Mixing mode AT85C51SND3B (2) bit in APCON1 and loading data using the (1) , the 151 ...
Page 152
... An 8-band bar-graph equalizer allows dynamic audio volume report inside 8 frequency bands. To read the level of each band, first select the band by setting the EQBS2:0 bits in APEBS from 000b (lowest frequency band) to 111b (highest frequency band) then get the 5-bit band level by reading EQLEV4:0 bits in APELEV. AT85C51SND3B 152 DVx4:0 Gain Value ...
Page 153
... The interrupt is requested each time one of the sources is asserted. Figure 73. Audio Processor Interrupt System 7632C–MP3–11/06 APREQI APINT.0 APREQE APIEN.0 APRDYI APINT.1 APRDYE APIEN.1 ACLIPI APINT.2 ACLIPE APIEN.2 APEVTI APINT.3 APEVTE APIEN.3 APGPI3:0 APINT.7:4 APGPE3:0 APIEN.7:4 AT85C51SND3B Audio Processor Interrupt Request EAUP IEN0.6 153 ...
Page 154
... Audio Codec The audio codec is controlled by four registers as detailed in Figure 74: Figure 74. Audio Codec Block Diagram The audio output system of AT85C51SND3B1 & AT85C51SND3B2 is based on a pair of Audio Outputs sigma-delta D/A converter used to convert the audio data with high linearity and high AT85C51SND3B1 & ...
Page 155
... Low/high voltage 50 K Ω drive 1 High voltage 32 Ω drive AISSEL Selection 0 Line Inputs 1 Microphone Input AIPG2:0 Gain Value AIPG2:0 000 0 dB 010 AT85C51SND3B AORG4:0 Gain Value AOLG4:0 Gain Value -8 dB 01110 -22 dB -10 dB 01111 -24 dB -12 dB 10000 -26 dB -14 dB 10001 -28 dB ...
Page 156
... Line Inputs Preamplifier Gain In AT85C51SND3B1 & AT85C51SND3B2, when Line Inputs are selected as output source (e.g. FM decoder playback) two preamplifier gain values can be applied by set- ting or clearing AILPG bit in ACIPG according to Table 161. Table 161. Audio Codec Line Inputs Preamplifier Gain In addition, voltage supply function for an electret type microphone is integrated deliver- Microphone Bias ing High bias (1 ...
Page 157
... 256 · 384 · CSPOL = 0 Left Channel CSPOL = 1 Left Channel 2 S Justification by setting JUST4:0 = 00001, and more than 16-bit LSB justifica- AT85C51SND3B 0 1 DSIZE ADICON0.3 CSPOL ADICON0.4 Data Converter JUST4:0 ADICON1.4:0 Right Channel Right Channel 2 S format, JUST4:0 bits in ADICON1 ...
Page 158
... DCLK DDAT DSEL DCLK DDAT DSEL DCLK DDAT DSEL DCLK DDAT Registers Table 165. AUCON Register AUCON (1.F1h) – Audio Controller Control Register AT85C51SND3B 158 Left Channel LSB MSB B14 I2S Format with DSIZE = 0 and JUST4:0 = 00001. Left Channel 1 ...
Page 159
... Set to reset the audio buffer read pointer. 3 ABRPR Cleared by hardware when read pointer is reset. Can not be cleared by software. Audio Buffer Split Bit 2 ABSPLIT Set to configure the audio buffer as a double buffer. Clear to configure the audio buffer as a single buffer. AT85C51SND3B APCMD3 APCMD2 APCMD1 4 3 ...
Page 160
... Table 168. APSTA Register APSTA (1.EAh) – Audio Processor Status Register Reset Value = 0000 0000b Table 169. APINT Register APINT (1.F4h) – Audio Processor Interrupt Register Reset Value = 0000 0000b AT85C51SND3B 160 Bit Bit Number Mnemonic Description Audio Processor Load Enable Bit ...
Page 161
... Number Mnemonic Description 7-0 APT7:0 Audio Processor Timer Least Significant Byte APT15 APT14 APT13 APT12 Bit Bit Number Mnemonic Description 7-0 APT15:8 Audio Processor Timer Intermediate Significant Byte. AT85C51SND3B APEVTE ACLIPE APRDYE APT3 APT2 APT1 APT11 ...
Page 162
... Table 175. APBDVOL, APMDVOL, APTDVOL Registers APBDVOL, APMDVOL, APTDVOL (2.F3h, 2.F4h, 2.F5h) – Audio Processor Bass, Medium, Treble Digital Volume Registers Reset Value = 0001 1111b Table 176. APEBS Register APEBS (2.F6h) - Audio Processor Equalizer Band Select Register AT85C51SND3B 162 APT23 ...
Page 163
... Reserved 7-4 - The value read from these bits is always 0. Do not set these bits. Always Cleared 3 0 This bit is permanently cleared by hardware to allow INC APEBS without affecting bits 7-4. Equalizer Band Selection 2-0 EQBS2:0 000b: lowest frequency band to 111b highest frequency band. AT85C51SND3B 163 ...
Page 164
... Clear to select the AT85C51SND3B0: Reserved The value read from this bit is always 0. Do not set this bit. AT85C51SND3B1 and AT85C51SND3B2: Audio Output Source Select Bit Set to select the audio processor as output source. AOSSEL Clear to select the line inputs as output source. 1 ...
Page 165
... Table 179. ACAUX Register (AT85C51SND3B1 and AT85C51SND3B2 only) ACAUX (2.E4h) – Audio Codec Auxiliary Register Reset Value = 0000 0000b Table 180. ACORG Register (AT85C51SND3B1 and AT85C51SND3B2 only) ACORG (2.EBh) – Audio Codec Right Output Gain Register Reset Value = 0000 0000b 7632C–MP3–11/06 ...
Page 166
... Mnemonic Description Reserved 7-4 - The value read from these bits is always 0. Do not set these bits. AT85C51SND3B1 and AT85C51SND3B2: Audio Input Line Preamplifier Gain Refer to Table 161 for gain value. 3 AILPG AT85C51SND3B0: Reserved The value read from this bit is always 0. Do not set this bit. ...
Page 167
... ASC7:0 Bits content depends on the audio codec firmware AS0S7 AS0S6 AS0S5 AS0S4 Bit Bit Number Mnemonic Description Audio Stream Status Byte 0 7-0 AS0S7:0 Bits content depends on the audio codec firmware. AT85C51SND3B JUST3 JUST2 JUST1 ASC3 ASC2 ASC1 4 3 ...
Page 168
... Table 187. ASSTA1 Register ASSTA1 (2.E3h) – Audio Stream Status Register 1 Reset Value = 0000 0000b Table 188. ASSTA2 Register ASSTA2 (2.E9h) – Audio Stream Status Register 2 Reset Value = 0000 0000b AT85C51SND3B 168 AS1S7 AS1S6 AS1S5 AS1S4 Bit Bit Number Mnemonic Description ...
Page 169
... Nand Flash The AT85C51SND3B derivatives implement a hardware Nand Flash Controller (NFC) embedding the following features: Controller • • • • • • • • • Functional overview As shown in Figure 78 the NFC architecture is based on six hardware units: • • • • • ...
Page 170
... The configuration is done by writing a descriptor byte by byte in the NFCFG register. The NF descriptor is composed of eight bytes (detailed in Table 189). The first byte written is byte 0. After writing a descriptor, a new one can be written to the NFC. Table 189. Configuration Descriptor Content AT85C51SND3B 170 IOVDD VDD NFCLE ...
Page 171
... SmartMedia/XD Card Enable Bit 0 SMCEN Set to enable SMC support. Clear to disable SMC support Bit Bit Number Mnemonic Description Reserved 7-2 - The value read from these bits is always 0. Do not set these bits. AT85C51SND3B NDB4 - - PDEV2 PDEV1 PDEV0 ...
Page 172
... DEV is the device number. SMC shall always be connected on device 3. Table 194 summarizes the possible configurations: if DEV is a device that does not comply with the configuration allowed, an illegal interrupt is triggered. AT85C51SND3B 172 Bit Bit ...
Page 173
... A read or a write in NFADC resets A9:8 to 00h. 01h selects the 2nd half zone, i.e. the 256-511 range in the data zone. 10h selects the spare zone, i.e. the 512-527 range in the data zone. AT85C51SND3B Comment No NF memory is selected The SMLCK signal can not be used in this configuration, the SMLCK bit is irrelevant ...
Page 174
... The NFADR register is used to select the raw address, i.e. the page address. The NFC uses that information to verify if the block is protected or not. Both kind of information are reset after a read of a write of the NFCMD register. A read in NFADC or NFADR returns an unexpected value. AT85C51SND3B 174 NFCLK / 2 NFCEx ...
Page 175
... The NFADC register is particularly suitable to read and poll the nand flash(es) status register. TRS Description [1.5; 0.5] Cycle 0 NFRE asserted during 1.5 clock period and deasserted during 0.5 clock period. [1.0;1.0] Cycle 1 NFRE asserted during 1 clock period and deasserted during 1 clock period. AT85C51SND3B Write data 175 ...
Page 176
... In all the previous examples, the NFCE line is asserted low and de-asserted at the end of the cycle. This allows minimizing the power consumption. Figure 80 shows a read access in a 512B page. Note that the NFCE must be held low Access Example during the access time for that kind of memory: AT85C51SND3B 176 Assembly code: mov #, direct NFCLK / 2 NFCEx ...
Page 177
... A page is composed of 512 contiguous data bytes (NDB= 1), followed by a spare zone of 16 bytes. Data zone “2kB” NF page A page is composed of 1024 contiguous data bytes (NDB= 4), followed by a spare zone of 64 bytes. Data zone AT85C51SND3B manual return in read mode NFD CMD CE ACT ...
Page 178
... ECCRDYE bit which is the ECC ready interrupt enable bit. Table 197 summarizes the spare zone behavior according to those control bits. Following section give detail on the management modes. Table 197. Spare Zone Management Modes AT85C51SND3B 178 Offset Description 0-1 User Data Area ...
Page 179
... ECC FIFO). The READ or WRITE bits must be set (write in NFACT) to resume the data transfer, until the end of the page or an STOP action. The firmware shall also re-initialize the ECC FIFO by writing to NFECC. AT85C51SND3B 179 ...
Page 180
... The Security Unit provides hardware mechanisms to protect NF content from any firm- ware crash and prevent data loss and provides data recovery capability through ECC management. AT85C51SND3B 180 read the ECC FIFO, (keeping the ECCs in memory), re-initialize it, resume the data transfer, and to write all the ECC bytes at the end of the page. ...
Page 181
... If FPB is lower than LPB, the protected area is a contiguous area starting from FPB to LPB. If FPB is higher than LPB, there are two protected areas: any block address that is below LPB and any block address that is above FPB. If FPB is equal to LPB, all the flash is protected.This is the default behavior. AT85C51SND3B 181 ...
Page 182
... For example, if the byte read at offset 1921 (starting from page is E3 (wrong) instead of A3: • • • Table 200. ECC Error Descriptor Table 201. ECC Error Identification Byte AT85C51SND3B 182 Block 0 Block 0 FPB LPB protected LPB FPB FPB < ...
Page 183
... The value read from these bits is always 0. 5-3 SHFB2:0 Second Half Fail Bit Flag 2-0 FHFB2:0 First Half Fail Bit Flag (1) 1. SMCD bit is not relevant until SMC management is enabled. IOVDD R PU SMINS SMCD NFSTA.7 AT85C51SND3B SHFB0 FHFB2 FHFB1 in NFSTA. SMCTI NFINT.4 0 FHFB0 183 ...
Page 184
... Processing interrupts are generated when: • • • Exception Interrupts are generated when the following events are met: • AT85C51SND3B 184 (1) 1. SDWP bit is not relevant until SMC management is enabled and a card is present in the socket (SMCD = 0). SMLCK SMCTI NFINT ...
Page 185
... Nand Flash Logical Address 2-byte Data FIFO Read Mode Reading from this register resets the FIFO manager logical block address. 7-0 NFLAD7:0 Write Mode Write 2 bytes of data (MSB first) to update the NFC logical block address according to Table 198. AT85C51SND3B NFGD3 NFGD2 NFGD1 ...
Page 186
... NFCON (1.9Bh) – Nand Flash Controller Control Register Table 206. NFERR Register NFERR (1.9Ch) – Nand Flash Controller ECC Error Information Register Reset Value = 0000 0000b Table 207. NFADR Register NFADR (1.9Dh) – Nand Flash Controller Row Address Register Reset Value = 0000 0000b AT85C51SND3B 186 ...
Page 187
... Reserved 7-5 - The value read from these bits is always 0. Do not set these bits. Extension Bits 4-3 EXT1:0 Refer to Table 193 for the bit description. Action Bits 2-0 ACT2:0 Refer to Table 193 for the bit description. AT85C51SND3B NFCAD3 NFCAD2 NFCAD1 CMD3 ...
Page 188
... Reset Value = 0000 0000b Table 212. NFDATF Register NFDATF (1.A3h) – Nand-Flash Controller Data Access and Fetch Next Data Register Reset Value = 0000 0000b Table 213. NFSTA Register NFSTA (1.98h) – Nand Flash Controller Status Register AT85C51SND3B 188 DATD7 DATD6 ...
Page 189
... ECCERRI Set by hardware when a bad ECC is seen. Shall be cleared by software. Stop Interrupt Flag Set by hardware when a running (NFRUN not running (NFRUN STOPI transition is met (end of page, end of data transfer, …) Shall be cleared by software. AT85C51SND3B NFED3 NFED2 NFED1 4 ...
Page 190
... Table 216. NFIEN Register NFIEN (1.A6h) – Nand Flash Controller Interrupt Enable Register Reset Value = 0000 0000b Table 217. NFUDAT Register NFUDAT (1.A7h) – Nand Flash Controller User Data Register Reset Value = 0000 0000b AT85C51SND3B 190 SMCTE Bit Bit Number ...
Page 191
... Most significant byte of the Byte Position counter BP7 BP6 BP5 BP4 Bit Bit Number Mnemonic Description Nand Flash Position Low Byte 7-0 BP7:0 Least significant byte of the Byte Position counter. AT85C51SND3B BP11 BP10 BP9 BP3 BP2 BP1 0 ...
Page 192
... MMC controller interrupt sources. These blocks are detailed in the following sections. Figure 86 shows the external components to add for connecting a MMC card to the AT85C51SND3B. SDDAT0 and SDCMD signals are connected to pull-up resistors. Value of these resistors is detailed in the Section “DC Characteristics”, page 242. Figure 85. MMC Controller Block Diagram Figure 86 ...
Page 193
... RFMT bit in MMCON0 register to indicate the response size expected. CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do not include CRC7. AT85C51SND3B CRC7 Generator MMINT.5 EOCI MMSTA ...
Page 194
... In case of time-out the command controller and its internal state machine may be reset by setting and clearing the CCR bit in MMCON2 register. This time-out may be disarmed when receiving the response. AT85C51SND3B 194 Command Transmission ...
Page 195
... MMCON0.3 HFRI HFRS MMINT.2 MMSTA.0 DBSIZE1:0 Bus Size 0 1-bit SDDAT0 data bus. 1 4-bit SDDAT3:0 data bus. 2-3 Reserved for future use, do not program these values. AT85C51SND3B Data Converter 1-bit/4-bit -> // DBSIZE1:0 MMCON2.4:3 CRC16 Generator DATA Line DATEN DATDIR BLEN11:0 MMCON1.2 MMCON1.3 MMCON1.7:4 ...
Page 196
... FIFO or half FIFO becomes empty (WFRS or HFRS set) before loading new data. In case both FIFO are empty, card clock is automatically frozen stopping card data transfer thanks to the controller automatic flow control. Note: AT85C51SND3B 196 Register Description MMBLP7:0 Block Size LSB: BLEN11:8 MMCON1 ...
Page 197
... To address all card types, this delay can be programmed using WR some cards do not respect MMC specification, and the busy status is reported too late on the dat0 line, considering the N st tus of the card must be asked with a card command. AT85C51SND3B parameter. So CBUSY flag is not set. In this case, sta- 197 ...
Page 198
... DATEN = 1 FIFO Filling write 16 data to MMDAT FIFO Empty? HFRS = 1? FIFO Filling write 8 data to MMDAT No More Data To Send? Send STOP Command a. Polling mode AT85C51SND3B 198 Data Stream Data Stream Initialization Transmission ISR Start Transmission FIFO Empty? DATEN = 1 HFRI = 1? Unmask FIFO Empty HFRM = 0 ...
Page 199
... According to the MMC specification data transmission from the card starts after the access time delay (formally N mand. To avoid any locking of the MMC controller when card does not send its data (e.g. physically removed from the bus), a time-out timer must be launched to recover 7632C–MP3–11/06 AT85C51SND3B Data Block Data Block Initialization Transmission ISR ...
Page 200
... MMDAT No More Data To Receive? Send STOP Command a. Polling mode AT85C51SND3B 200 1. An enabled DFC transfer always takes precedence on a C51 transfer under soft- ware responsibility not to read from MMDAT register while a DFC transfer is enabled. Data Stream Initialization ...