at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 86
at85c51snd3b
Manufacturer Part Number
at85c51snd3b
Description
Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3B.pdf
(270 pages)
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General Operating Modes
Introduction
Power-On and Reset
86
AT85C51SND3B
Figure 50. USB Connection
After a hardware reset, the USB controller is disabled.
When enabled, the USB controller has to run the Device Controller or the Host Control-
ler. This is performed using the ID detection.
•
•
The software anyway has to select the mode (Host, Device) in order to access to the
Device controller registers or to the Host controller registers, which are multiplexed. For
example, even if the USB controller has detected a Device mode (pin ID high), the soft-
ware shall select the device mode (bit HOST cleared), otherwise it will access to the
host registers. This is also true for the Host mode.
Figure 51 shows the USB controller main states after power-on.
Figure 51. USB Controller Reset State Machine
USB Controller state after an hardware reset is ‘Reset’. In this state:
•
•
•
•
•
If the ID pin is not connected to ground, the ID bit is set by hardware (internal pull up
on the UID pad) and the USB Device controller is selected.
The ID bit is cleared by hardware when a low level has been detected on the ID pin.
The Device controller is then disabled and the Host controller enabled.
USBE is not set,
the macro clock is stopped in order to minimize the power consumption
(FRZCLK=1),
the macro is disabled,
the pad is in the suspend mode,
the Host and Device USB controllers internal states are reset.
R
UVSS
UB
C
UB
UBIAS
Clock stopped
Generator
Dev ice
OTG 5V
FRZCLK=1
Macro off
USBE=1
ID=1
Out
VBUS
ON
USBE=0
GND
Reset
D+
D-
ID
USBE=1
ID=0
VSS
USBE=0
RESET
USBE=0
Host
HW
USBE=0
UVCC
UID
<any other
state>
R
R
UFT
UFT
7632C–MP3–11/06
UVCON
DPF
DMF
DPH
DMH
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