at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 111

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Standard Mode with AUTOSW
Using the DFC with AUTOSW
Using the DFC without
AUTOSW
Abort
7632C–MP3–11/06
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If the endpoint uses 2 banks, the second one can be read by the HOST while the current
is being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may
be already ready (free) and TXINI is set immediately.
In this mode (AUTOSW set), the flow operation is the same as Section “Standard Mode
without AUTOSW”, page 110, with the exception that the CPU does not have to free the
bank (FIFOCON cleared): this will automatically be done when the CPU fills the bank.
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A clear of FIFOCON does not have any effects in this mode.
In this mode (AUTOSW set, DFC programmed), the data are handled by the DFC with-
out any intervention from the CPU. The flow is:
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The bank switching is automatically done: when a bank is filled, it is freed and the switch
occurs. If the End Of Transfer occurs while the bank is not filled, the CPU has the
responsibility to free it.
The CPU shall not use UEDATX or the byte counter BYCT in this mode. A clear of
FIFOCON does not have any effects in this mode.
In this mode (AUTOSW=0, DFC programmed), the data are handled by the DFC but the
CPU have to acknowledge each bank written:
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An “abort” stage can be produced by the host in some situations:
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The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort
is to perform the following operations:
The CPU can free the bank by clearing FIFOCON when all the data are written, that
is:
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EPINTx (TXINE set, TXINI set) or polling on TXINI=1 or FIFOCON=1,
The CPU acknowledges the interrupt by clearing TXINI,
The CPU can write the data to the current bank (write in UEDATX) while RWAL is
set.
programming of the DFC,
poll End Of Transfer from the DFC.
programming of the DFC,
EPINTx (TXINE set, TXINI set) or polling on TXINI=1 or FIFOCON=1,
The CPU acknowledges the interrupt by clearing TXINI,
poll the wait of the transfer: (while RWAL is set: wait),
Clear FIFOCON which frees the bank and switch to the next one.
In a control transaction: ZLP data OUT received during a IN stage,
In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint
during a IN stage on the IN endpoint
…
after “N” write into UEDATX
as soon as RWAL is cleared by hardware.
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