at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 218
at85c51snd3b
Manufacturer Part Number
at85c51snd3b
Description
Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3B.pdf
(270 pages)
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Receiver
Flow Control
218
AT85C51SND3B
As shown in Figure 110, the receiver is based on a character handler taking care of
character integrity check and feeding the reception shift register filling itself a 16-byte
data FIFO managed by the FIFO and flow controller.
Figure 110. Receiver Block Diagram
The reception flow can be controlled by hardware using the RTS pin. The goal of the
flow control is to inform the external transmitter when the Rx FIFO is full of a certain
amount of data. Thus the transmitter can stop sending characters. RTS usage and so
associated flow control is enabled using RTSEN bit in SFCON.
To support transmitter that has stop latency, a threshold can be programmed to allow
characters reception after RTS has been deasserted. The threshold can be pro-
grammed using RTSTH1:0 in SFCON according to Table 242. As soon as enough data
has been read from the Rx FIFO, RTS is asserted again to allow transmitter to continue
transmission. To avoid any glitch on RTS signal, an hysteresis on 1 data is imple-
mented.
Figure 111 shows a reception example using a threshold of 4 data and a host transmit-
ter latency of 3 characters.
Figure 111. Reception Flow Control Waveform Example
Table 242. RTS Deassertion Threshold
Index
FIFO
RXD
RTS
RTSTH1
0
0
1
1
CLOCK
0
BRG
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
1
RTSTH0
2
0
1
0
1
3
16-byte FIFO
Rx Shift Reg
SBUF Rx
4
Description
RTS deasserted when Rx FIFO is full.
RTS deasserted when 2 data can still be loaded in Rx FIFO.
RTS deasserted when 4 data can still be loaded in Rx FIFO.
RTS deasserted when 8 data can still be loaded in Rx FIFO.
OVERSF3:0
5
SFCON.7:4
6
7
8
9
SINT.0
SINT.4
10 11
OEI
RI
FIFO & Flow Controller
Character Handler
C13 C14 C15
12 13
Host Stop
Latency
RTSEN
SCON.2
SINT.3
PEI
14 15 14 13 12
CPU Read
RTSTH1:0
SCON.1:0
SINT.2
FEI
11
10
C16 C17 C18 C19
11 12 13
7632C–MP3–11/06
Host Stop
Latency
RTS
RXD
C20
14
15
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