pxb4330 Infineon Technologies Corporation, pxb4330 Datasheet - Page 190

• Manufacturer Part Number: pxb4330
• Description: Ics For Communications
• Manufacturer: Infineon Technologies Corporation

Data Sheet
7.4.5
Timing of the Synchronous Dynamic RAM Interface is simplified as all signals are refer-
enced to the rising edge of SYSCLK. In Figure 7-9, it can be seen that all signals output
by the PXB 4330 E ABM have identical delay times with reference to the clock. When
reading from the RAM, the PXB 4330 E ABM samples the data within a window at the
rising clock edge.
Figure 7-9
Table 7-13
No.
105
106
Table 7-14
No.
110
110A
DQ(31:0), output
DQ(31:0), input
A(10:0), RAS,
CAS, CS, WE
Parameter
Setup time RDATx Input before
SYSCLK rising (read cycles)
Hold time RDATx Input after SYSCLK
rising (read cycles)
Parameter
T
F
SYSCLK
SYSCLK
SDRAM Interface
SYSCLK
Generic SDRAM Interface Timing Diagram
SSRAM Interface AC Timing Characteristics (cont’d)
SDRAM Interface AC Timing Characteristics
: Period SYSCLK
: Frequency SYSCLK
7-190
111
Min
5
3
Min
19.3
115
110
Limit Values
Limit Values
113
114
116
Typ
Typ
Electrical Characteristics
112
Max
Max
52
PXB 4330
Unit
ns
ns
Unit
ns
MHz
09.99