pxb4330 Infineon Technologies Corporation, pxb4330 Datasheet - Page 95

• Manufacturer Part Number: pxb4330
• Description: Ics For Communications
• Manufacturer: Infineon Technologies Corporation

•
Register 12 TCT0
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Register WAR.DwordSel(1:0) = ’00’:
Bit
Bit
BufNrtMax(7:0)
BufNrtEPD(7:0)
Data Sheet
15
7
TCT Transfer Register 0
14
Maximum Buffer Fill Threshold for a non-real-time traffic class
EPD threshold for a non-real-time traffic class configuration
configuration (register TCT1, DwordSel=00, RTind=0).
The first cell exceeding this threshold is discarded and if also PPD
is enabled for this traffic class (register TCT1, DwordSel=00,
PPDen=1) PPD is applied on a per connection (LCI) basis.
The threshold is defined with a granularity of 256 cells:
Threshold = BufNrtMax(7:0) * 256 Cells
(register TCT1, DwordSel=’00’, RTind=0).
If the buffer fill exceeds this threshold and EPD is enabled for this
traffic class (register TCT1, DwordSel=00, EPDen=1) EPD is
applied on a per connection (LCI) basis.
The threshold is defined with a granularity of 256 cells:
Threshold = BufNrtEPD(7:0) * 256 Cells
6
Read/Write
0000
TCT0
Written and Read by CPU to maintain the TCT table;
the meaning of register TCT0 depends on the bit-field
’DWordSel’ in WAR;
H
13
5
32
H
BufNrtEPD(7:0)
BufNrtMax(7:0)
12
4
6-95
11
3
10
2
Register Descriptions
9
1
PXB 4330
8
0
09.99