is62wv12816bll-55b2i Integrated Silicon Solution, Inc., is62wv12816bll-55b2i Datasheet

is62wv12816bll-55b2i

Manufacturer Part Number

is62wv12816bll-55b2i

Description

128k X 16 Low Voltage, Ultra Low Power Cmos Static Ram

Manufacturer

Integrated Silicon Solution, Inc.

Datasheet

1.IS62WV12816BLL-55B2I.pdf (17 pages)

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IS62WV12816ALL

IS62WV12816BLL

128K x 16 LOW VOLTAGE,

ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 45ns, 55ns, 70ns

• CMOS low power operation

• TTL compatible interface levels

• Single power supply

• Fully static operation: no clock or refresh

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• 2CS Option Available

• Lead-free available

FUNCTIONAL BLOCK DIAGRAM

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. G

07/18/06

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

– 36 mW (typical) operating

– 9 µW (typical) CMOS standby

– 1.65V--2.2V V

– 2.5V--3.6V V

required

(62WV12816BLL)

(62WV12816ALL)

Lower Byte

Upper Byte

I/O8-I/O15

I/O0-I/O7

A0-A16

VDD

GND

CS2

CS1

DECODER

CIRCUIT

CONTROL

CIRCUIT

DATA

I/O

1-800-379-4774

DESCRIPTION

The

speed, 2M bit static RAMs organized as 128K words by 16

bits. It is fabricated using

technology. This highly reliable process coupled with

innovative circuit design techniques, yields high-

performance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS2 is LOW

(deselected) or when CS1 is LOW, CS2 is HIGH and both

LB and UB are HIGH, the device assumes a standby mode

at which the power dissipation can be reduced down with

CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs. The active LOW Write Enable

(WE) controls both writing and reading of the memory. A

data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

The IS62WV12816ALL and IS62WV12816BLL are packaged

in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and

44-Pin TSOP (TYPE II).

ISSI

MEMORY ARRAY

COLUMN I/O

IS62WV12816ALL/ IS62WV12816BLL are high-

128K x 16

ISSI

's high-performance CMOS

ISSI

JULY 2006

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