is62wv6416all Integrated Silicon Solution, Inc., is62wv6416all Datasheet - Page 10

• Manufacturer Part Number: is62wv6416all
• Description: 64k X 16 Low Voltage, Ultra Low Power Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS62WV6416ALL,
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
V
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
least one of the LB and UB inputs being in the LOW state.
WC
SCS1/
AW
HA
SA
PWB
PWE
SD
HD
HZWE
LZWE
DD
-0.2V/V
ADDRESS
(3)
t
(3)
SCS2
LB, UB
DOUT
DD
CS1
CS2
DIN
WE
-0.3V and output loading specified in Figure 1.
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
(1,2)
IS62WV6416BLL
(CS1 Controlled, OE = HIGH or LOW)
t
DATA UNDEFINED
SA
t
AW
t
HZWE
t
t
SCS2
SCS1
t
t
t
PWB
PWE
WC
Min.
45
35
35
35
35
20
HIGH-Z
—
0
0
0
5
(1,2)
45ns
t
SD
(Over Operating Range)
Integrated Silicon Solution, Inc. — www.issi.com
DATA-IN VALID
Max.
—
—
—
—
—
—
—
—
—
20
—
t
HA
t
t
LZWE
HD
Min.
45
45
55
45
40
25
—
0
0
0
5
55 ns
Max.
—
—
—
—
—
—
—
—
20
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
01/14/08
Rev. C