is42s16100-7tli Integrated Silicon Solution, Inc., is42s16100-7tli Datasheet - Page 28

• Manufacturer Part Number: is42s16100-7tli
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16100
Interval Between Read Command
A new command can be executed while a read cycle
is in progress, i.e., before that cycle completes. When
the second read command is executed, after the CAS
latency has elapsed, data corresponding to the new read
command is output in place of the data due to the previous
read command.
CAS latency = 2, burstlength = 4
28
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the
data for the previous write command.
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
CLK
DQ
CLK
DQ
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
t
CCD
D
IN
t
CCD
B0
D
OUT
D
A0
IN
B1
D
OUT
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two read command (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
B0
IN
Integrated Silicon Solution, Inc. — www.issi.com
B2
D
OUT
D
B1
IN
B3
D
OUT
B2
D
OUT
B3
ccd
ccd
) must be
) must be
01/28/08
Rev. D