is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 30

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16128 can output data continuously from the
burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IS42S16128 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t
command.
30
IS42S16128
CAS latency = 2, burst length = full page
CAS latency = 3, burst length = full page
COMMAND
COMMAND
CLK
CLK
RAS
I/O
I/O
max.) following the burst stop
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
READ A0
READ A0
D
OUT
A0
D
D
OUT
OUT
A0
A0
After the period (t
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance state.
This period (t
is one, two clock cycle when the CAS latency is two and
three clock cycle when the CAS latency is three.
Integrated Silicon Solution, Inc. — 1-800-379-4774
D
D
OUT
OUT
A1
A0
CAS Latency
BURST STOP
BURST STOP
D
D
RBD
OUT
OUT
BST
BST
t
RBD
) is one clock cycle when the CAS latency
A2
A1
RBD
t
) required for burst data output to
RBD
D
D
OUT
OUT
t
RBD
A2
A3
D
OUT
HI-Z
3
3
A3
ISSI
HI-Z
2
2
03/13/00
Rev. A
®