is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 32

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Burst Data Interruption U/LDQM Pins
(Write Cycle)
Burst data input can be temporarily interrupted (muted )
during a write cycle using the U/LDQM pins. Regardless
of the CAS latency, as soon as one of the U/LDQM pins
goes HIGH, the corresponding externally applied input
data will no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the
burst read cycle operates normally, but the write cycle
only writes a single data item for each write cycle. The
CAS latency and DQM latency are the same as in normal
mode.
32
IS42S16128
CAS latency = 2, 3
CAS latency = 2, burst length = 4
COMMAND
COMMAND
I/O8-I/O15
I/O0-I/O7
CLK
UDQM
LDQM
I/O
CLK
WRITE (CA=A, BANK 0)
DATA MASK (UPPER BYTE)
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
WRITE A0
WRITE A0
D
D
t
DMD=0
IN
IN
A0
A0
D
IN
The IS42S16128 will revert to accepting input as soon as
that pin is dropped to LOW and data will be written to the
device. This input control operates independently on a
byte basis with the UDQM pin controlling upper byte input
(pin I/O8 to I/O15) and the LDQM pin controlling the lower
byte input (pins I/O0 to I/O7).
Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, inparticular,
incrementing of the internal burst counter continues.
A1
Integrated Silicon Solution, Inc. — 1-800-379-4774
D
IN
A2
D
D
IN
IN
A3
A3
Don’t Care
ISSI
03/13/00
Rev. A
®