is43lr16800f-6bl Integrated Silicon Solution, Inc., is43lr16800f-6bl Datasheet

is43lr16800f-6bl

Manufacturer Part Number

is43lr16800f-6bl

Description

2m X 16bits X 4banks Mobile Ddr Sdram

Manufacturer

Integrated Silicon Solution, Inc.

Datasheet

1.IS43LR16800F-6BL.pdf (42 pages)

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BOSTOCK HK LIMITED

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is43lr16800f-6blI

Manufacturer:

ISSI, Integrated Silicon Solution Inc

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10 000

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Rev. 00A | Dec. 2010

Description

16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted

on a 16-bit bus. The double data rate architecture is essentially a 2

words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.

The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are

compatible with LVCMOS.

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or

effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to

its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

The IS43/46LR16800F is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x

Features

• JEDEC standard 1.8V power supply.

• VDD = 1.8V, VDDQ = 1.8V

• Four internal banks for concurrent operation

• MRS cycle with address key programs

• Fully differential clock inputs (CK, /CK)

• All inputs except data & DM are sampled at the rising

• Data I/O transaction on both edges of data strobe

• Bidirectional data strobe per byte of data (DQS)

• DM for write masking only

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

edge of the system clock

- CAS latency 2, 3 (clock)

- Burst length (2, 4, 8, 16)

- Burst type (sequential & interleave)

2M x 16Bits x 4Banks Mobile DDR SDRAM

www.issi.com

- dram@issi.com

prefetch architecture with an interface designed to transfer two data

• 64ms refresh period (4K cycle)

• Auto & self refresh

• Concurrent Auto Precharge

• Maximum clock frequency up to 166MHZ

• Maximum data rate up to 333Mbps/pin

• Power Saving support

• LVCMOS compatible inputs/outputs

• 60-Ball FBGA package

- PASR (Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Deep Power Down Mode

- Programmable Driver Strength Control by Full Strength

or 1/2, 1/4, 1/8 of Full Strength

IS43/46LR16800F

Advanced Information

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