w9425g6jb Winbond Electronics Corp America, w9425g6jb Datasheet - Page 14

• Manufacturer Part Number: w9425g6jb
• Manufacturer: Winbond Electronics Corp America

7.8
7.9
7.10 Mode Register Operation
7.10.1 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4, and 8 words.
resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh
operation.
Two types of Power Down Mode can be performed on the device: Active Standby Power Down
Mode and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled
resulting in low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking
CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at
next CLK rising edge. Refer to the diagrams for Power Down Mode.
DDR SDRAM input clock frequency can be changed under following condition:
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a
minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency
between minimum and maximum operating frequency specified for the particular speed grade.
During an input clock frequency change, CKE must be held LOW. Once the input clock frequency
is changed, a stable clock must be provided to DRAM before precharge power down mode may be
exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS
command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM
is ready to operate with new clock frequency.
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all
banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to
A12 and BA0, BA1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is
divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode
selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set
the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode
Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented
the extended function (DLL enable/Disable mode).
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
Power Down Mode
Input Clock Frequency Change during Precharge Power Down Mode
A2
0
0
0
0
1
A1
0
0
1
1
x
A0
0
1
0
1
x
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Publication Release Date: Oct. 08, 2010
BURST LENGTH
Reserved
Reserved
2 words
4 words
8 words
W9425G6JB
Revision A01