tza3017hw NXP Semiconductors, tza3017hw Datasheet
tza3017hw
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... DATA SHEET TZA3017HW 30 Mbits 3.2 Gbits/s A-rate fibre optic transmitter Product specification Supersedes data of 2002 Jan 16 INTEGRATED CIRCUITS 2003 May 14 ...
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... Physical interface IC in transmit channels Transponder applications Dense Wavelength Division Multiplexing (DWDM) systems. GENERAL DESCRIPTION The TZA3017HW is a fully integrated optical network transmitter, containing a clock synthesizer and a multiplexer with multiplexing ratios of 16:1, 10:1, 8:1 or 4:1. The A-rate feature allows the IC to operate at any bit rate between 30 Mbits/s and 3 ...
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... deep MUX FIFO TZA3017HW POWER-ON 2 CLOCK RESET SYNTHESIZER 2 1, 25, 33, 36, 41, 49, 58, 61, 64, 65, 68, 77, 80, 83, 87, 90, 93, 100 CCD V CCA V CCO V DD PRSCLO CREF LOL ...
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... CCD DOUTQ DOUT V CCD V CCO V EE CLKDIR UI PARERRQ PARERR V CCA 4 Product specification TZA3017HW PIN DESCRIPTION 40 parallel clock output 41 supply voltage (digital part) 42 reference clock input inverted 43 reference clock input 44 parity select (odd or even) 45 multiplexing ratio select 1 46 multiplexing ratio select 0 ...
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... SYMBOL CLOOPQ CLOOP V CCD D15Q D15 D14Q D14 D13Q D13 V CCD 5 Product specification TZA3017HW PIN DESCRIPTION 91 loop mode clock output inverted 92 loop mode clock output 93 supply voltage (digital part) 94 parallel data input 15 inverted 95 parallel data input 15 96 parallel data input 14 inverted ...
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... D06Q 16 D06 17 D05Q 18 D05 19 20 D04Q D04 21 D03Q 22 23 D03 CCD 25 2003 May 14 TZA3017HW Fig.2 Pin configuration. 6 Product specification TZA3017HW V CCA 75 PARERR 74 PARERRQ CLKDIR CCO 68 V CCD 67 DOUT 66 DOUTQ 65 V CCD 64 V CCD 63 MD1 ...
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... The function and content of the I 2 described in Section “I C-bus registers”. Some functions in the TZA3017HW can be controlled either by the I a designated pin. The method required is specified by an extra bit named I2C<pin name> in the corresponding 2 I C-bus register, for example, bit I2CPARITY in register MUXCNF2 ...
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... LOL up PHASE- CHARGE-PUMP R FREQUENCY down DETECTOR LOOP FILTER CALCULATOR N[8:0] K[21:0] Fig.3 Block diagram of the clock synthesizer. Table 4 Truth table for bits REFDIV in I REFDIV TZA3017HW OCTAVE DIVIDER VCO M AND MAIN DIVIDER N 9 FRACTION 9 22 MGW561 SYNTHCNF SDH/SONET R REFERENCE DIVISION FREQUENCY ...
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... Once the octave and M division factor are known, the 2 4 division factors for N and K can be calculated for a given 3 8 reference frequency using the Flowchart in Fig. Product specification TZA3017HW corresponding octaves BIT RATE PROTOCOL (Mbits/s) 3125.00 2970.00 FEC 2666.06 2488.32 2380.00 2125.00 1485.00 1380.00 1300.00 1250 ...
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... yes Write K j into registers B3H, B4H and B5H Convert N to binary and write into registers B1H and B2H END 10 Product specification TZA3017HW 0.75 ? yes 0 decimal to binary conversion of fractional part ...
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... Mbits -------------------------------------------------------- - f 19.44 MHz ref bit rate M R 3012 Mbits 1 1 n.k = --------------------------------------- - = ----------------------------------------------- - f ref 11 Product specification TZA3017HW 2488.32 Mbits/s) (STM16/OC48 link at pins CREF and CREFQ is 38.88 MHz, ref 0.5 = 0.6428571, and N is 109.3106996 = 2 C-bus register FRACN2 = 146.9268293 20.50 MHz 0.5 = 0.4268293, and N 2 C-bus 2 C-bus 2 C-bus ...
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... The multiplexer comprises a high-speed input register, a 4-bit deep First In First Out (FIFO) elastic buffer, a parity check circuit and a multiplexing tree. Parallel data bus clocking schemes The TZA3017HW supports both co-directional and contra-directional clocking schemes for the parallel data bus; see Figs 7 and 8. The clocking scheme is selected by 2 ...
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... PARITY TX_PARITY PARITYQ 16 D00 to D15 TX_DATA 16 D00Q to D15Q PICLK TX_CLK PICLKQ POCLK TX_CLK_SRC POCLKQ FIFORESET CREF Fig.7 Co-directional clocking. 13 Product specification TZA3017HW C-bus register MUXCNF1 POPHASE PHASE SHIFT TZA3017HW MGW565 system clock 0 90 180 270 ...
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... Table C-bus control mode, the default multiplexing ratio 2 C-bus register is 16:1. For multiplexing ratios 16:1, 8:1 and 4:1, the MSB is transmitted first. For multiplexing ratio 10:1, the LSB is transmitted first. 14 Product specification TZA3017HW TZA3017HW MGW566 system clock (pin 13 C-bus ...
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... May 14 BITS MUX (REG. MUXCNF1) LOW 00 HIGH 01 LOW 10 HIGH 11 PICLK D00-D15 PARITY PARERR PARITY ERROR Fig.9 Parity timing. 15 Product specification TZA3017HW MULTIPLEXING ACTIVE INPUTS RATIO LSB to MSB 4:1 D06 to D09 8:1 D04 to D11 10:1 D03 to D12 16:1 D00 to D15 2 C-bus MDB063 ...
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... To keep the number of external components required to a minimum, most of the common standards: LVPECL, CML 2 C-bus and LVDS are terminated internally; see Fig.10. V CCD CML termination Fig.10 Rail-to-rail input termination configurations. 16 Product specification TZA3017HW . CC V CCD LVPECL termination MDB062 ...
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... Chapters “Characteristics” and “Limiting values”. 2 C-bus All external components should be surface mounted, with a preferable size of 0603 or smaller. The components must be mounted as close to the IC as possible. 17 Product specification TZA3017HW 2 C-bus register IOCNF1 (address CAH). 2 C-bus register IOCNF0 2 C-bus interface standard ...
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... The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. data line change stable; of data data valid allowed Fig.11 Bit transfer. 18 Product specification TZA3017HW 2 C-BUS C-bus is for 2-way, 2-line communication between MBC621 ...
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... The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. SDA SCL MASTER TRANSMITTER / RECEIVER 2003 May 14 Fig.12 Definition of start and stop conditions. SLAVE SLAVE TRANSMITTER / RECEIVER RECEIVER Fig.13 System configuration. 19 Product specification TZA3017HW SDA SCL P STOP condition MBC622 MASTER MASTER TRANSMITTER / TRANSMITTER RECEIVER MBA605 ...
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... In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition; see Fig.17 START condition Fig.14 Acknowledgment on the I 20 Product specification TZA3017HW not acknowledge acknowledge 8 9 clock pulse for acknowledgement MBC602 2 C-bus. ...
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... C-bus, the device which should respond is addressed first. The address byte is LSB MSB R/W 1 Fig.15 Slave and register addresses. acknowledge acknowledge from slave from slave R/W MSB SLAVE REGISTER ADDRESS Fig.16 Write protocol. 21 Product specification TZA3017HW LSB Register address MDB070 acknowledge from slave MSB LSB DATA one byte transferred MDB386 ...
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... R/W MSB LSB 1 A DATA A first byte Fig.17 Read protocol. 2 C-bus control mode by setting pin UI HIGH or leaving pin UI open circuit. 22 Product specification TZA3017HW acknowledge acknowledge (1) (1) from master from master MSB LSB A DATA A P last byte MDB387 ...
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... X X reserved high junction temperature junction temperature junction temperature < 130 C FIFO overflow or underflow overflow or underflow normal operation reserved 23 Product specification TZA3017HW DEFAULT READ/ VALUE WRITE R R 0000 0000 W 0110 1001 W 0001 1000 W 0000 0000 W ...
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... Loss of Lock (LOL) 1 out of lock (loss of lock condition lock X X reserved high junction temperature junction temperature junction temperature < 130 C FIFO overflow or underflow overflow or underflow normal operation reserved 24 Product specification TZA3017HW PARAMETER NAME LOL TALARM 130 C OVERFLOW ...
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... I C-bus interface via pins ENLINQ and/or ENLOUTQ default value 25 Product specification TZA3017HW PARAMETER DESCRIPTION BUSSWAP PARITY I2CPARITY PICLKINV PDINV ENLIN ENLOUT I2CLOOPMODE NAME ...
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... I C-bus interface via pin CLKDIR multiplexing ratio 16:1 10:1 8:1 4:1 multiplexing ratio programming 2 via I C-bus interface via pins MUXR0 and MUXR1 default value 26 Product specification TZA3017HW PARAMETER NAME POCLKEN POPHASE POCLKINV CLKDIR I2CLKDIR MUXR I2CMUXR ...
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... DESCRIPTION main divider division factor MSB default value DESCRIPTION main divider division factor LSB default value 27 Product specification TZA3017HW PARAMETER NAME FIFORESET I2CFIFORESET PIHYST PARAMETER NAME DIV_M PARAMETER NAME DIV_N PARAMETER NAME DIV_N ...
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... R; reference frequency 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz default value 28 Product specification TZA3017HW PARAMETER NAME DIV_K NILFRAC PARAMETER NAME DIV_K PARAMETER NAME DIV_K PARAMETER NAME INITSYNTH ...
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... LVPECL mode: floating; CML mode: AC-coupled LVPECL mode: standard; CML mode: DC-coupled parallel output mode Current Mode Logic (CML) Low Voltage Positive Emitter Coupled Logic (LVPECL default value 29 Product specification TZA3017HW PARAMETER NAME MFS PRSCLOINV PRSCLOEN MFOUTTERM MFOUTMODE ...
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... Product specification TZA3017HW PARAMETER NAME CININV DININV CDINSWAP COUTINV DOUTINV CDOUTSWAP COUTENA DOUTENA ...
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... INT output polarity inverted; active LOW output normal; active HIGH output pin INT output mode standard CMOS output open-drain output default value 31 Product specification TZA3017HW PARAMETER NAME RFS CLOOPINV DLOOPINV RFOUTTERM CDLOOPSWAP PARAMETER NAME MLOL MTALARM MOVERFLOW ...
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... TZA3017HW FEATURES IN PRE-PROGRAMMED MODE Although the TZA3017HW is primarily intended programmed via the I C-bus, many of the TZA3017HW functions can be accessed either via the I control mode (pin UI HIGH), or via the external chip pins in pre-programmed mode (pin UI LOW). The TZA3017HW functions that are accessible in pre-programmed mode ...
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... In compliance with JEDEC standards JESD51-5 and JESD51-7. 2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. 2003 May 14 PARAMETER PARAMETER 33 Product specification TZA3017HW MIN. MAX. UNIT 0.5 3 0.5 V ...
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... 20% to 80% 80% to 20% between differential 50 crossovers between differential 40 crossovers MUX 16:1, 8:1, 4:1 30 MUX 10:1; note 5 30 single-ended Product specification TZA3017HW MIN TYP MAX 1.2 2.4 215 270 345 430 250 318 380 478 0.82 1.1 1.25 1.66 0.2V CC ...
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... termination LVPECL floating; 700 single-ended with 50 external load 20% to 80% 300 80% to 20% 300 single-ended single-ended Product specification TZA3017HW MIN TYP MAX 50 60 0. 1000 30 100 120 2 1 400 850 ...
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... HIGH-level nH 2003 May 14 CONDITIONS SDH/SONET requirement 20 see Table 0.8V 0.05V 1.3 0.6 0.6 0.6 0 100 0 1.3 0 0.1V 0.2V 36 Product specification TZA3017HW MIN TYP MAX 20 R 19 100 0.9 300 300 400 UNIT ppm MHz ...
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... MHz f = 250 kHz to 5 MHz STM16/OC48 mode; notes 7 and kHz to 20 MHz kHz to 20 MHz MHz to 20 MHz 2 C-bus register MUXTIMING (address FDH) should be programmed with 0000.0100 37 Product specification TZA3017HW MIN TYP MAX ...
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... May 14 LVPECL standard CML AC 5 Fig.18 Supply current per parallel output. LVPECL 5 Fig.19 Output voltage swing of parallel output. 38 Product specification TZA3017HW MBL556 LVPECL floating CML value of address C8H, bit 3 to bit 0 MDB064 DEFAULT CML 10 15 value of address C8H, bit 3 to bit 0 ...
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... May 14 CML AC 5 Fig.20 Supply current per serial output. DEFAULT 5 Fig.21 Output voltage swing of serial output. 39 Product specification TZA3017HW MDB065 CML value of address CBH, bit 3 to bit 0 MDB066 10 15 value of address CBH, bit 3 to bit 0 ...
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... Fig.23 Parallel output floating LVPECL mode (DC-coupled). 2003 May transmission OUT OUTQ on-chip off-chip Fig.22 Parallel output standard LVPECL mode OUT OUTQ on-chip 40 Product specification TZA3017HW V term 2 V optional AC coupling lines to high- 50 impedance 50 input 50 50 MBL562 transmission lines ...
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... I swing in 2003 May coupling OUT OUTQ on-chip off-chip V CC 100 100 OUT OUTQ on-chip off-chip Fig.25 Parallel output CML mode (AC-coupled). 41 Product specification TZA3017HW V bias transmission 50 50 lines to high- 50 impedance 50 input MBL561 V bias 50 50 transmission lines to high- 50 impedance ...
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... V CC 100 100 OUT OUTQ on-chip off-chip Fig.26 Parallel output CML mode (DC-coupled OUT OUTQ on-chip off-chip Fig.27 Serial output CML mode (AC-coupled). 42 Product specification TZA3017HW 50 50 transmission lines to high- 50 impedance 50 input MBL564 V bias 50 50 transmission lines to high- 50 ...
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... The timing is measured from the crossover point of the reference signal to the crossover point of the input. 2003 May OUT OUTQ on-chip off-chip Fig.28 Serial output CML mode (DC-coupled). t h(co) t su(co) valid data Fig.29 Parallel bus co-directional timing. 43 Product specification TZA3017HW 50 50 transmission lines to high- 50 impedance 50 input MDB069 MBL581 ...
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... COUT, CLOOP DOUT, DLOOP The timing is measured from the crossover point of the reference signal to the crossover point of the output. 2003 May 14 valid data t su(contra) Fig.30 Parallel bus contra-directional timing. t D-C Fig.31 RF output timing. 44 Product specification TZA3017HW t h(contra) MBL582 MBL583 ...
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... scale (1) ( 0.20 14.1 7.1 14.1 7.1 16.15 0.5 0.09 13.9 6.1 13.9 6.1 15.85 REFERENCES JEDEC JEITA 45 Product specification TZA3017HW detail 16.15 0.75 1 0.2 0.08 0.08 15.85 0.45 EUROPEAN PROJECTION SOT638 (1) ( 1.15 1.15 7 0.85 0.85 0 ISSUE DATE 01-03-30 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 46 Product specification TZA3017HW ...
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... Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 May 14 (1) not suitable not suitable suitable not recommended not recommended 47 Product specification TZA3017HW SOLDERING METHOD (2) WAVE REFLOW suitable (3) suitable suitable (4)(5) suitable ...
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... Product specification TZA3017HW DEFINITION These products are not Philips Semiconductors ...
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... I Philips. This specification can be ordered using the code 9398 393 40011. 2003 May components conveys a license under the Philips’ system provided the system conforms to the I 49 Product specification TZA3017HW 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors 30 Mbits 3.2 Gbits/s A-rate fibre optic transmitter 2003 May 14 NOTES 50 Product specification TZA3017HW ...
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... Philips Semiconductors 30 Mbits 3.2 Gbits/s A-rate fibre optic transmitter 2003 May 14 NOTES 51 Product specification TZA3017HW ...
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Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited ...