tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 18

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Interrupt register
The following events are recorded by setting the
appropriate bit(s) in I
(address 00H):
When register INTERRUPT is polled by an I
action, any set bits are reset. If a condition is still active,
the corresponding bit remains set.
Status register
The current status of the conditions that are recorded by
register INTERRUPT are indicated by setting the
appropriate bit(s) in I
(address 01H). A bit is set only for the period that the
condition is active and resets when the condition clears.
Register STATUS is polled by an I
Interrupt generation
An interrupt is generated if an interrupt condition sets a bit
in I
bit is not masked by I
(address CCH). Only the high junction temperature
interrupt bit is not masked by default. A generated interrupt
is indicated by an active logic level at pin INT.
2003 May 14
handbook, full pagewidth
Loss of lock
High junction temperature
FIFO overflow or underflow.
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
2
C-bus register INTERRUPT (address 00H) and if the
2
2
2
C-bus register INTERRUPT
C-bus register STATUS
C-bus register INTMASK
SDA
SCL
2
C-bus read action.
2
C-bus read
data valid
data line
stable;
Fig.11 Bit transfer.
18
allowed
change
of data
The active output level used is set by bit INTPOL in
I
LOW level. Bit INTOUT sets the output mode at pin INT to
either open-drain or to standard CMOS. The default is
open-drain. An active LOW output in open-drain mode
allows several receivers to be connected together,
and requires only one 3.3 k pull-up resistor.
CHARACTERISTICS OF THE I
The I
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
Bit transfer
Refer to Fig.11. One data bit is transferred during each
clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as control
signals.
2
C-bus register INTMASK. The default is an active
2
C-bus is for 2-way, 2-line communication between
MBC621
2
C-BUS
TZA3017HW
Product specification