tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 7

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The TZA3017HW converts parallel input data into serial
output data having a bit rate from 30 Mbits/s up to
3.2 Gbits/s. An internal clock synthesizer synchronizes the
internal oscillator to an external reference frequency.
The parallel input data is multiplexed at ratios of 16:1,
10:1, 8:1 or 4:1.
Choice of user interface control
The TZA3017HW can be controlled either via the I
or using programming pins DR0 to DR2. Pin UI selects the
user interface required. I
functionality are enabled when pin UI is either open circuit
or connected to V
when pin UI is connected to V
Table 1 Truth table for pin UI
In I
I
actions, pin CS must be HIGH. When pin CS is LOW, the
programmed configuration remains active, but pins SDA
and SCL are ignored. This allows several TZA3017HWs in
the application with the same I
selected separately. The I
TZA3017HW is shown in Table 2.
Table 2 I
The function and content of the I
described in Section “I
the TZA3017HW can be controlled either by the I
a designated pin. The method required is specified by an
extra bit named I2C<pin name> in the corresponding
I
register MUXCNF2. The default is enable by pin.
If the application has no I
operate with reduced functionality in pre-programmed
mode. In pre-programmed mode, pins DR0 to DR2 are
standard CMOS inputs that allow the selection of up to
eight pre-programmed bit rates using an external
reference clock frequency of 19.44 MHz; see Table 3.
2003 May 14
2
2
LOW
HIGH
C-bus pins SDA and SCL. During I
C-bus register, for example, bit I2CPARITY in
A6
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
1
UI
2
C-bus control mode, the chip is configured using
pre-programmed
I
A5
2
0
2
C-bus control
C-bus address of the TZA3017HW
MODE
A4
1
CC
. Pre-programmed mode is enabled
2
C-bus registers”. Some functions in
A3
2
0
2
C-bus control and A-rate
2
C-bus control, the IC has to
C-bus address of the
PIN 54
EE
DR0
2
CS
A2
C-bus address to be
1
; see Table 1.
2
C-bus registers are
2
C-bus read or write
A1
PIN 53
0
DR1
SDA
A0
0
2
C-bus or
PIN 52
2
DR2
SCL
C-bus
R/W
X
7
Table 3 Truth table for selecting bit rate in
After power-up, the TZA3017HW initiates a Power-On
Reset (POR) sequence to restore the default settings of
the I
The default settings are shown in Table 10.
Clock synthesizer
Refer to Fig.3. The clock synthesizer is a fractional N-type
synthesizer which provides the A-rate
It consists of a Voltage Controlled Oscillator (VCO), octave
divider M, main divider N, fractional divider K, reference
divider R, Phase Frequency Detector (PFD), integrated
loop filter, Loss Of Lock (LOL) detection circuit, and a
prescaler output buffer. The internal VCO is phase-locked
to a reference clock signal of typically 19.44 MHz applied
to pins CREF and CREFQ.
The clock synthesizer has a 22-bit fractional N capability
which allows any combination of bit rate and reference
frequency between 18 x R and 21 x R MHz, where R is
the reference division factor. The LSB (bit k[0]) of the
fractional divider, should be set to logic 1 to avoid limit
cycles. These are cycles of less than maximum length that
generate spurs in the frequency spectrum. This leaves
21 bits (k[21:1]) available for programming the fraction,
allowing a resolution frequency of approximately 10 Hz at
a fixed reference frequency.
The clock synthesizer does not require any external
components, allowing easier application use.
To comply with most transmission standards, the
reference frequency must be very accurate with minimum
phase noise in order to synthesize a pure RF clock signal
that complies with the strictest requirements for jitter
generation; see Section “Jitter performance”.
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
DR2
2
C-bus registers, irrespective of the level on pin UI.
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
pre-programmed mode (pin UI = V
DR1
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
DR0
STM1/OC3
STM4/OC12
STM16/OC48
STM16
GE
10GE
Fibre Channel
Fibre Channel
PROTOCOL
FEC
TZA3017HW
Product specification
TM
functionality.
EE
BIT RATE
2488.32
2666.06
1250.00
3125.00
1062.50
2125.00
(Mbits/s)
)
155.52
622.08