tza3005h NXP Semiconductors, tza3005h Datasheet - Page 22

• Manufacturer Part Number: tza3005h
• Description: Sdh/sonet Stm1/oc3 And Stm4/oc12 Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Forward clocking
It is sometimes necessary to ‘forward clock’ data in an
SDH/SONET system. When this is the case, the input
parallel data clock (TXPCLK) and the reference clock
(REFCLK/REFCLKQ) from which the high speed serial
clock is synthesized will both originate from the same clock
source. This section explains how to configure the
TZA3005H to operate in this mode.
The connections required for forward clocking are shown
in Fig.13. There are no timing specifications for the phase
relationship between REFCLK and TXPCLK.
The TZA3005H can handle any phase relationship
between these two input clocks if they are derived from the
same clock source. The TZA3005H internal transmitter
logic must be synchronized by asserting a master reset
(MRST).
2000 Feb 17
handbook, halfpage
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
Fig.11 PECL output termination scheme
(V
CC
83.3
= 5.0 V).
R1
V CC = 5.0 V
GND
125
R3
R2
83.3
R4
125
MGK654
TXSD/TXSCLK
TXSDQ/TXSCLKQ
22
Reverse clocking
In many cases, a reverse clocking scheme is used where
the upstream logic is clocked by the TZA3005H using
SYNCLKDIV (see Fig.14). There is no requirement
specification for the propagation delay from SYNCLKDIV
to TXPCLK because the TZA3005H can handle any phase
relationship between these two signals. The TZA3005H
internal transmitter logic must be synchronized by
asserting a master reset (MRST).
PECL output termination
The PECL outputs have to be terminated with 50
connected to V
Thevenin termination can be used as shown in Figs 11
and 12.
handbook, halfpage
Fig.12 PECL output termination scheme
(V
GND
CC
CC
= 3.3 V).
2.0 V. If this voltage is not available, a
V CC = 3.3 V
R1
127
R3
82.5
R2
127
R4
82.5
MGS978
Product specification
TZA3005H
TXSD/TXSCLK
TXSDQ/TXSCLKQ