zl2103 Intersil Corporation, zl2103 Datasheet

Page 1

... IC that combines an integrated synchronous step-down DC/DC converter with key power management functions in a small package, resulting in a flexible and integrated solution. The ZL2103 can provide an output voltage from 0.54V to 5.5V (with margin) from an input voltage between 4.5V and 14V. Internal low r synchronous power MOSFETs enable the ...

Page 2

... Typical Application Circuit The following application circuit represents a typical implementation of the ZL2103. For PMBus operation recommended to tie the enable pin (EN) to SGND. † DDC Bus ENABLE PGOOD †† SMBus Notes: ‡ Ferrite bead is optional for input noise suppression. ...

Page 3

... I/O 23, 24 BST PWR 27, 28, 29 VDDP PWR 30 VDDS PWR 3 ZL2103 ZL2103 (36 LD QFN) TOP VIEW PG 1 DGND 2 ZL2103 SYNC 3 VSET 4 36-Pin QFN SCL 6 SDA 7 Exposed Paddle SALRT 8 Connect to SGND FC 9 FIGURE 4. Power-good. This pin transitions high 100ms after output voltage stabilizes within regulation band. ...

Page 4

... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ZL2103. For more information on MSL please see techbrief TB363. 4 ZL2103 Regulated bias from internal 7V low-dropout regulator (return is PGND). Decouple with a 4.7µ ...

Page 5

... I C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Output Sequencing .25 Fault Spreading .26 2 Monitoring via I C/SMBus .26 Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 ZL2103 FN6966.5 May 3, 2011 ...

Page 6

... Output Voltage Adjustment Range (Note 11) Output Voltage Setpoint Resolution Vsen Output Voltage Accuracy Vsen Input Bias Current Soft-start Delay Duration Range (Note 13) 6 ZL2103 Thermal Information Thermal Resistance (Typical QFN (Notes Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Storage Temperature Range .-55°C to +150°C ...

Page 7

... UVLO Hysteresis UVLO Delay Power-good V Threshold OUT Power-good V Hysteresis OUT Power-good Delay 7 ZL2103 = V = 12V -40°C to +85°C unless otherwise noted. (Note 10) Typical values are at T DDS A (Continued) CONDITIONS Turn-on delay (precise mode) (Notes 13, 14) Turn-on delay (normal mode) (Note 15) ...

Page 8

... Maximum duty cycle is limited by the equation MAX_DUTY(%) = [1 - (150×10 19 1/f , where f is the switching frequency 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8 ZL2103 = V = 12V -40°C to +85°C unless otherwise noted. (Note 10) Typical values are at T DDS A (Continued) CONDITIONS Factory default 2 ...

Page 9

... +25° (V) DDS FIGURE 7. LOW-SIDE DS(ON) 9 ZL2103 For some applications, ZL2103 operating conditions (input voltage, output voltage, switching 75 100 FIGURE 6. HIGH-SIDE r = 0.3A WITH T FIGURE 8. MAXIMUM CONVERSION RATIO, DDS +125°C. IN DDP DDS J 1 ...

Page 10

... Integrated sub-regulation circuitry enables single supply operation from any external supply between 4.5V and 14V with no secondary bias supplies needed. The ZL2103 can also be configured to operate from a 3. standby supply when the main power rail is not present, allowing the user to configure and/or read diagnostic information from the device when the main power has been interrupted or is disabled ...

Page 11

... COMMUNICATION COMMUNICATION SCL SCL SA SA The ZL2103 integrates two N-channel power MOSFETs the top control MOSFET and QL is the bottom synchronous MOSFET. The amount of time that fraction of the total switching period is known as the duty cycle D, which is described by Equation ≈ ...

Page 12

... The block diagram for the ZL2103 is illustrated in Figure 10. In this circuit, the target output voltage is regulated by connecting the VSEN pin directly to the output regulation point. The VSEN signal is then compared to an internal reference voltage that had been set to the desired output voltage level by the user ...

Page 13

... IN TABLE 3. ZL2103 START-UP SEQUENCE DESCRIPTION Input voltage is applied to the ZL2103’s VDD pins (VDDP and VDDS). The device will check for values stored in its internal memory. This step is also performed after a Restore command. The device loads values configured by the multi-mode pins. ...

Page 14

... OUT expired. These features may be used as part of an overall inrush 2.3 current management strategy or to control how fast a load IC is 2.4 turned on. The ZL2103 gives the system designer several options for precisely and independently controlling both the delay and 2.5 ramp time periods. 2.6 The soft-start delay period begins when the EN pin is asserted 2 ...

Page 15

... Table 6. The value of this resistor is measured upon start-up or Restore and will not change if the resistor is varied after power has been applied to the ZL2103 (see Figure 14 FIGURE 14. SS PIN RESISTOR CONNECTIONS The soft-start delay and ramp times can also be set to custom ...

Page 16

... PG are met and when the PG pin is actually asserted. This feature is commonly used instead of an external reset controller to signal the power supply is at its target voltage prior to enabling any powered circuitry. By default, the ZL2103 PG delay is set to 1ms and may be changed using the I interface as described in AN2033. ...

Page 17

... TABLE 8. SWITCHING FREQUENCY SELECTION SYNC PIN LOW OPEN HIGH Resistor If the user wishes to run the ZL2103 at a frequency not listed in Table 8, the switching frequency can be set using an external resistor connected between SYNC and SGND using SYNC Table 9. TABLE 9. R ...

Page 18

... Use the DCR specified in the inductor manufacturer’s data sheet. = × DCR I LDCR Lrms 18 ZL2103 I is given by Equation 6: Lrms = I Lrms where I OUT core loss of the selected inductor. Since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor data sheet ...

Page 19

... The ZL2103 operates as a voltage-mode synchronous buck B controller with a fixed frequency PWM scheme. Although the ZL2103 uses a digital control loop, it operates much like a traditional analog PWM controller. Figure simplified block diagram of the ZL2103 control loop, which differs from an analog control loop only by the constants in the PWM and compensation blocks ...

Page 20

... In the ZL2103, the compensation zeros are set by configuring the 2 FC pin or via the I C/SMBus interface once the user has calculated the required settings. This method eliminates the inaccuracies due to the component tolerances associated with using external resistors and capacitors required with traditional analog controllers ...

Page 21

... IC is enabled. Certain applications require that the converter not be allowed to sink current during start pre-bias condition exists at the output. The ZL2103 provides pre- bias protection by sampling the output voltage prior to initiating an output ramp. ...

Page 22

... Output Overcurrent Protection The ZL2103 can protect the power supply from damage if the output is shorted to ground overload condition is imposed on the output. Once the current limit threshold has been selected (see “Current Sensing and Current Limit Threshold Selection” on page 19), the user may determine the desired course of action in response to the fault condition ...

Page 23

... PMBus. Voltage Margining The ZL2103 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. The MGN command is set by driving the ...

Page 24

... The ZL2103 provides an I C/SMBus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. The ZL2103 can be 2 used with any standard 2-wire I C host device. In addition, the device is compatible with SMBus version 2.0 and includes an SALRT line to help mitigate bandwidth limitations related to continuous fault monitoring ...

Page 25

... CFG pin), the devices must be assigned sequential SMBus addresses with no missing addresses in the chain. This mode will also constrain each device to have a phase offset according to its SMBus address as described in section “Phase Spreading” on page 25. 25 ZL2103 TABLE 16. CFG PIN CONFIGURATIONS FOR SEQUENCING AND TRACKING R CFG Low ...

Page 26

... I C/SMBus interface. Snapshot™ Parametric Capture The ZL2103 offers a special feature that enables the user to capture parametric data during normal operation or following a fault. The Snapshot functionality is enabled by setting bit 1 of MISC_CONFIG to 1. See ...

Page 27

... FN6966.2 Added “LatchupTested to JESD78” to “Absolute Maximum Ratings” on page 6. 01/22/2010 FN6966.1 Changed order information parts from “ZL2103ALAF, ZL2103ALAFT, ZL2103ALAFTK” TO “ZL2103ALAN, ZL2103ALANT, ZL2103ALANTK” 12/15/2009 FN6966.0 Initial release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks ...

Page 28

... Package Outline Drawing L36.6x6C 36 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/10 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 60 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ZL2103 36X 0.60 ± 0.10 BOTTOM VIEW MAX 1. SIDE VIEW (36X 0. REF ( 36X 0.80 ) DETAIL " ...