zl2103 Intersil Corporation, zl2103 Datasheet - Page 11

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zl2103

Manufacturer Part Number
zl2103
Description
3a Digital-dc Synchronous Step-down Dc/dc Converter
Manufacturer
Intersil Corporation
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
INTERSIL
Quantity:
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The ZL2103 integrates two N-channel power MOSFETs; QH is the
top control MOSFET and QL is the bottom synchronous MOSFET.
The amount of time that QH is on as a fraction of the total
switching period is known as the duty cycle D, which is described
by Equation 1:
During time D, QH is on and V
inductor. The output current ramps up as shown in Figure 11.
When QH turns off (time 1-D), the current flowing in the inductor
must continue to flow from the ground up through QL, during which
the current ramps down. Since the output capacitor C
low impedance at the switching frequency, the AC component of the
inductor current is filtered from the output voltage so the load sees
nearly a DC voltage.
The maximum conversion ratio is shown in Figure 9. Typically,
buck converters specify a maximum duty cycle that effectively
limits the maximum output voltage that can be realized for a
given input voltage and switching frequency. This duty cycle limit
ensures that the low-side MOSFET is allowed to turn on for a
minimum amount of time during each switching cycle, which
enables the bootstrap capacitor to be charged up and provide
adequate gate drive voltage for the high-side MOSFET.
D ≈
V
V
OUT
IN
SALRT
SALRT
VTRK
VTRK
SYNC
SYNC
>
>
DDC
DDC
SDA
SDA
SCL
SCL
FC
FC
SA
SA
RESET
RESET
COMMUNICATION
COMMUNICATION
IN
11
PG
PG
SYNC
SYNC
GEN
GEN
– V
POWER MANAGEMENT
POWER MANAGEMENT
OUT
EN
EN
COMPENSATOR
COMPENSATOR
COMPENSATOR
COMPENSATOR
REF
REF
is applied across the
MGN
MGN
DIGITAL
DIGITAL
PLL
PLL
DIGITAL
DIGITAL
INPUT VOLTAGE BUS
INPUT VOLTAGE BUS
CFG
CFG
FIGURE 10. ZL2103 BLOCK DIAGRAM
OUT
SS
SS
ADC
ADC
ADC
ADC
exhibits
D-PWM
D-PWM
ADC
ADC
NVM
NVM
VSET
VSET
(EQ. 1)
ZL2103
MUX
MUX
I
I
SENSE
SENSE
+
+
VDD
VDD
Σ
Σ
HS FET
HS FET
DRIVER
DRIVER
DRIVER
DRIVER
LS FET
LS FET
SENSOR
SENSOR
-
-
TEMP
TEMP
V
IN
LDO
LDO
I
I
- V
SENSE
SENSE
-V
OUT
OUT
0
FIGURE 11. INDUCTOR WAVEFORM
VSEN
VSEN
BST
BST
SW
SW
D
Time
>
>
1 - D
V
V
OUT
OUT
IL
IL
I
O
V
PK
May 3, 2011
FN6966.5

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