atmega103 ATMEL Corporation, atmega103 Datasheet - Page 68
atmega103
Manufacturer Part Number
atmega103
Description
Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA103.pdf
(141 pages)
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Data Reception
68
ATmega103(L)
Figure 42. UART Receiver
The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times
the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as
the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample
1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver samples the
RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be
logical “1”s, the start bit is rejected as a noise spike and the Receiver starts looking for
the next 1-to-0 transition.
If, however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 8, 9 and 10. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
Transmitter Shift Register as they are sampled. Sampling of an incoming character is
shown in Figure 43.
RXD
XTAL
PIN CONTROL
GENERATOR
BAUD RATE
LOGIC
BAUD X 16
DATA RECOVERY
LOGIC
DATA BUS
REGISTER (UCR)
UART CONTROL
/16
STORE UDR
DATA BUS
BAUD
RXC
IRQ
REGISTER (USR)
REGISTER (UDR)
SHIFT REGISTER
UART STATUS
UART I/O DATA
10(11)-BIT RX
0945I–AVR–02/07
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