cop8tac9 National Semiconductor Corporation, cop8tac9 Datasheet
cop8tac9
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cop8tac9 Summary of contents
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... ROM and Flash Memory and related features such as In- Device included in this datasheet: Flash Program Device Memory (kbytes) COP8TAB9 2 COP8TAC9 4 2.0 Features KEY FEATURES n 2k bytes or 4k bytes Flash Program Memory, with Security Feature, organized in 512 byte pages that can be erased or written individually n 128 bytes volatile RAM n 2.25V – ...
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Block Diagram 4.0 Ordering Information COP8 TA C Family and Program Feature Set Memory Indicator Size Note: The user, utilizing the COP8TAx9 Flash based devices during devel- opment for applications to be produced ...
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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagrams ................................................................................................................................... 6 6.0 Architectural Overview ................................................................................................................................. 8 6.1 EMI REDUCTION ...................................................................................................................................... 8 6.2 IN-SYSTEM PROGRAMMING .................................................................................................................. 8 6.3 ...
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IDLE MODE ........................................................................................................................................... 29 13.3 MULTI-INPUT WAKE-UP ...................................................................................................................... 30 14.0 Interrupts .................................................................................................................................................. 31 14.1 INTRODUCTION ................................................................................................................................... 31 14.2 MASKABLE INTERRUPTS ................................................................................................................... 32 14.3 VIS INSTRUCTION ............................................................................................................................... 33 14.3.1 VIS Execution .................................................................................................................................. 34 14.4 NON-MASKABLE INTERRUPT ............................................................................................................ 35 14.4.1 Pending ...
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Revision History ....................................................................................................................................... 57 22.0 Physical Dimensions ................................................................................................................................ 58 Table of Contents (Continued) 5 www.national.com ...
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Connection Diagrams Top View 28 Pin Plastic SOIC WIDE Package See NS Package Number M28B www.national.com Top View 44 Pin LLP Package See NS Package Number LQA44A 20 Pin Plastic SOIC WIDE Package 20047504 6 20047502 20047505 Top View ...
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Port Type Alt. Function L0 I/O MIWU/SDA L1 I/O MIWU/SCL L2 I/O L3 I/O L4 I/O L5 I/O L6 I/O L7 I/O G0 I/O G1 I/O WDOUT G2 I/O G3 I/O G4 I ...
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Architectural Overview 6.1 EMI REDUCTION The COP8TAB9/TAC9 devices incorporate circuitry that guards against electromagnetic interference - an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) ...
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Architectural Overview 6.5.5 Register Set Three memory-mapped pointers handle register indirect ad- dressing and software stack pointer functions. The memory data pointers allow the option of post-incrementing or post- decrementing with the data movement instructions (LOAD/ EXCHANGE). Fifteen (15) ...
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Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level (Human Body Model) (Machine Model) ...
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Electrical Characteristics AC Electrical Characteristics −40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Oscillator Frequency Crystal/Resonator, External Internal R/C Oscillator R/C Oscillator Frequency Variation Instruction Cycle Time ( Crystal/Resonator, ...
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Electrical Characteristics AC Electrical Characteristics −40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter SDA Hold Time (t ) Figure 4 SDAho SDA Valid Time (t ) Figure 4 SDAso Note 2: ...
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Electrical Characteristics 9.0 Pin Descriptions The COP8TAB9/TAC9 I/O structure enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance ...
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Pin Descriptions FIGURE 5. LLP Package Bottom View CKI is the clock input. This pin can be connected (in con- junction with CKO external crystal circuit to form a crystal oscillator external resistor for RC ...
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Pin Descriptions (Continued) L7 Multi-Input Wake-Up L6 Multi-Input Wake-Up L5 Multi-Input Wake-Up L4 Multi-Input Wake-Up L3 Multi-Input Wake-Up L2 Multi-Input Wake-Up (optional 1.8V compatible input) L1 Multi-Input Wake-Up or ACCESS.Bus Serial Clock (op- tional 1.8V compatible input) L0 Multi-Input ...
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... Memory Device Size (Flash)(Bytes) COP8TAB9 2048 COP8TAC9 4096 10.3 DATA MEMORY The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, ACCESS.Bus Interface and the various registers and counters associated with the timer, T1 ...
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... Example: The following sets a value in the Option Register and User Identification for a COP8TAC9HLQ7. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash Memory. .chip 8TAC ...
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Functional Description (Continued) WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Moni- tor bit set. The WATCHDOG ...
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Functional Description (Continued) FIGURE 13. Reset Timing (Power-On Reset Enabled) with V Tied to RESET CC 10.7 OSCILLATOR CIRCUITS There are five clock oscillator options available: fully internal R/C Oscillator, R/C Oscillator with external frequency deter- mination resistor, Crystal ...
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Functional Description (Continued) 20047525 FIGURE 15. Crystal Oscillator With External Bias Resistor With External Frequency Control Resistor (R/C+R) 20047527 10.7.2 Crystal Oscillator The Crystal Oscillator mode can be selected by program- ming Option Bit CKI is ...
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Functional Description (Continued) 10.8 CONTROL REGISTERS 10.8.1 CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode ...
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... When read- ing the Option register, 07FF (hex) should be placed into the address registers of COP8TAB9 devices and 0FFF (hex) should be placed into the address registers of COP8TAC9 devices. Registers ISPADHI and ISPADLO are cleared Reset. ...
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In-System Programming TABLE 10. PGMTIM Register Format (Continued ...
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In-System Programming (Continued) 11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET After programming the entire program memory, including options necessary to exit the Boot ROM and return to the Flash program memory for program execution. Upon receipt ...
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Timers The device contains a very versatile set of timers (T0 and T1). Timer T1 and associated autoreload/capture registers power up containing random data. 12.1 TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and ...
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Timers (Continued) 12.2 TIMER T1 One of the main functions of a microcontroller is to provide timing and counting capability for real-time control tasks. The COP8 family offers a very versatile 16-bit timer/counter structure, and two supporting 16-bit autoreload/capture ...
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Timers (Continued) FIGURE 21. Timer in External Event Counter Mode 12.5 MODE 3. INPUT CAPTURE MODE The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the input capture mode. In ...
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Timers (Continued) 12.6 TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent ...
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Power Save Modes second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may only be used ...
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Power Save Modes 13.3 MULTI-INPUT WAKE-UP The Multi-Input Wake-Up feature is used to exit from the HALT and IDLE modes. In addition, the Multi-Input Wake- Up/Interrupt feature may be used to generate edge-selectable external interrupts on ...
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Power Save Modes and LWKPND registers contain undefined values after reset, so software should clear these bits after reset to ensure that no spurious Wake-Up events or interrupts are left pending. 14.0 Interrupts 14.1 INTRODUCTION The device supports eleven ...
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Interrupts (Continued) 14.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The ...
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Interrupts (Continued) sponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. If more than one interrupt is active, the ...
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Interrupts (Continued) Arbitration Ranking (1) Highest Software (2) Reserved for NMI (3) External (4) Timer T0 (5) Timer T1 (6) Timer T1 (7) MICROWIRE/PLUS (8) ACCESS.Bus (9) Reserved (10) Reserved (11) Reserved (12) Reserved (13) Reserved (14) Reserved (15) ...
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Interrupts (Continued) 14.4 NON-MASKABLE INTERRUPT 14.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service ...
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Interrupts (Continued) . SERVICE: RBIT,EXPND,PSW . . . RET I 14.5 PORT C AND PORT L INTERRUPTS Ports C and L provides the user with an additional sixteen fully selectable, edge sensitive interrupts which are all vec- tored into ...
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WATCHDOG/Clock Monitor (Continued) TABLE 16. WATCHDOG Service Window Select (Continued) WDSVR WDSVR Clock Bit 7 Bit 6 Monitor (Lower-Upper Limits 256–32k 256–64k Clock Monitor Disabled ...
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WATCHDOG/Clock Monitor (Continued) • The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently, the de- vice inadvertently entering the HALT mode will be de- tected as a CLOCK MONITOR error (provided that the ...
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MICROWIRE/PLUS mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is in the idle phase. 16.2 MICROWIRE/PLUS MASTER MODE ...
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MICROWIRE/PLUS TABLE 20. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase Port G SK Phase G6 (SKSEL) Config. Bit Normal 0 Alternate 1 Alternate 0 Normal 1 FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase ...
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MICROWIRE/PLUS FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High 17.0 ACCESS.Bus Interface The ACCESS.Bus interface module (ACB two-wire serial interface compatible with the ACCESS.Bus physical layer. It permits easy interfacing ...
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ACCESS.Bus Interface (Continued) At each clock cycle, the slave can stall the master while it handles the previous data, or prepares new data. The slave can hold SCL low, to extend the clock-low period, on each bit transfer, or ...
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ACCESS.Bus Interface (Continued) 17.5 ACB SERIAL DATA REGISTER (ACBSDA) The ACBSDA register is a byte-wide, read/write shift register used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted ...
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ACCESS.Bus Interface (Continued) GCMEN The Global Call Match Enable bit enables the match of an incoming address byte to the general call address (Start Condition followed by address byte of 00) while the ACB is in slave mode. ACK ...
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Memory Map (Continued) Address Contents ADD REG A8 ISP Address Register Low Byte (ISPADLO) A9 ISP Address Register High Byte (ISPADHI) AA ISP Read Data Register (ISPRD) AB ISP Write Data Register (ISPWR Reserved B0 to ...
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Instruction Set (Continued) erand addressing modes and transfer-of-control addressing modes. Operand addressing modes are the various meth- ods of specifying an address for accessing (reading or writ- ing) data. Transfer-of-control addressing modes are used in conjunction with jump instructions ...
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Instruction Set (Continued) 19.3.2 Tranfer-of-Control Addressing Modes Program instructions are usually executed in sequential or- der. However, Jump instructions can be used to change the normal execution sequence. Several transfer-of-control ad- dressing modes are available to specify jump addresses. ...
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Instruction Set (Continued) Jump Absolute Long (JMPL) Jump Indirect (JID) Jump to Subroutine (JSR) Jump to Subroutine Long (JSRL) Jump to Boot ROM Subroutine (JSRB) Return from Subroutine (RET) Return from Subroutine and Skip (RETSK) Return from Interrupt (RETI) ...
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Instruction Set (Continued) 19.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JSRB Addr Jump SubRoutine Boot ROM JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No ...
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Instruction Set (Continued) Register [ (Note 8) 1 (Note 8) 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 8: = Memory location addressed directly. ...
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Nibble Lower 53 www.national.com ...
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... COP8-PGMA-44CF2 base pinout) KANDA’s Flash ISP COP8 USB ISP Programmer www.kanda.com Development Devices COP8TAB9 COP8TAC9 < *Cost: Free; VL= $100; L=$100-$300; M=$300-$1k; H=$1k-$3k; VH=$3k-$5k www.national.com Cost* Notes/Includes Free Assembler/ Linker/ Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc ...
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... WCOP8 IDE and Emulator Debugger, with Assembler/ on CD-ROM Linker/ Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation. Included with most tools from National. Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Expert Simulation tool with Graphical and Traditional user interfaces ...
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Development Support Programmers for: Design Development; Hardware Test; Pre-Production; Full Production. Product COP8 Flash COP8 Flash Emulators include in-circuit device programming capability during Emulators development. NiceMon National’s software Utilities "KANDAFlash" and "NiceMon" provide development Debugger, In-System-Programming for our Flash ...
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Development Support Vendor Home Office SofTec Microsystems Via Roma, 1 33082 Azzano Decimo (PN) Italy Tel: +39 0434 640113 Fax: +39 0434 631598 The following companies have approved COP8 programmers in a variety of configurations. Contact your vendor’s local ...
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... Physical Dimensions Order Number COP8TAB9HLQ8 or COP8TAC9HLQ8 Order Number COP8TAB9EMW8 or COP8TAC9EMW8 www.national.com inches (millimeters) unless otherwise noted LLP Package NS Package Number LQA44A SOIC Wide Package NS Package Number M28B 58 ...
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... Physical Dimensions Order Number COP8TAB9CMW8 or COP8TAC9CMW8 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. ...