cop8tac9 National Semiconductor Corporation, cop8tac9 Datasheet - Page 18

• Manufacturer Part Number: cop8tac9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
10.0 Functional Description
10.6.1 External Reset
The RESET input, when pulled low, initializes the device.
The RESET pin must be held low for a minimum of one
instruction cycle to guarantee a valid reset. Reset should be
long enough to ensure crystal start-up upon Power-Up, if the
Crystal Oscillator option has been selected.
RESET may also be used to cause an exit from the HALT
mode.
Any controller which features the capability for the soft-
ware to modify the contents of the Flash memory is
susceptible to inadvertent writes or erases any time V
is below the minimum guaranteed operating conditions,
the clock is running and the device is not held in Reset.
Flash memory is subject to corruption if the Reset se-
quence shown inFigure 11 is not applied to the RESET
input. For this reason, the use of external brownout
detection is strongly recommended. Any Reset circuit
must ensure that RESET is set high only after V
reaches V
when V
cal Characteristics.
A recommended reset circuit for this device is shown in
Figure 12.
(Continued)
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Moni-
tor bit set. The WATCHDOG and Clock Monitor circuits
are inhibited during reset. The WATCHDOG service win-
dow bits being initialized high default to the maximum
WATCHDOG service window of 64k T0 clock cycles. The
Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached
the minimum specified frequency at the termination of
reset. A Clock Monitor error will cause an active low output
on pin G1. This error output will continue until 16–32 T0
clock cycles following the clock frequency reaching the
minimum specified value, at which time the G1 output will
go high.
CC
falls to V
CC(min)
FIGURE 11. Reset vs Vcc
and RESET is set low immediately
CC(min)
as specified in the DC Electri-
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CC
CC
18
10.6.2 On-Chip Power-On Reset
The device generates an internal reset as V
voltage level above 2.0V. The on-chip reset circuitry is able
to detect both fast and slow rise times on V
between 20 µs and 10 ms).
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
the RESET pin should be connected to V
through a pull-up resistor. If forced operation from the Boot
ROM is anticipated, a pull-up resistor should be used so that
the ISP circuit can override the RESET circuit and force the
RESET pin low. The output of the power-on reset detector
will always preset the Idle timer to 00FF(256 t
the internal reset will be generated.
The internal reset will not be turned off until the Idle timer
underflows. The internal reset will perform the same func-
tions as external reset. The user is responsible for ensuring
that V
t
Power On Reset circuit will generate no additional internal
resets as long as V
The contents of data registers and RAM are unknown fol-
lowing the on-chip reset.
C
. After the underflow, the logic is designed such that the
FIGURE 12. Reset Circuit Using External Reset
CC
is at the minimum level for operating within the 256
CC
remains above 2.0V.
CC
CC
, either directly or
C
(V
CC
). At this time,
20047522
CC
rises to a
rise time