cop8tac9 National Semiconductor Corporation, cop8tac9 Datasheet - Page 23

• Manufacturer Part Number: cop8tac9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

11.0 In-System Programming
11.4 MANEUVERING BACK AND FORTH BETWEEN
FLASH MEMORY AND BOOT ROM
When using ISP, at some point, it will be necessary to
maneuver between the Flash program memory and the Boot
ROM, even when using customized ISP routines. This is
because it’s not possible to execute from the Flash program
memory while it’s being programmed.
Two instructions are available to perform the jumping back
and forth: Jump to Boot (JSRB) and Return to Flash (RETF).
The JSRB instruction is used to jump from Flash memory to
Boot ROM, and the RETF is used to return from the Boot
ROM back to the Flash program memory. See Section 19.0
Instruction Set for specific details on the operation of these
instructions.
The JSRB instruction must be used in conjunction with the
Key register. This is to prevent jumping to the Boot ROM in
the event of run-away software. For the JSRB instruction to
actually jump to the Boot ROM, the Key bit must be set. This
is done by writing the value shown in Table 11 to the Key
register. The Key is a 6 bit key and if the key matches, the
KEY bit will be set for 8 instruction cycles. The JSRB instruc-
tion must be executed while the KEY bit is set. If the KEY
does not match, then the KEY bit will not be set and the
JSRB will jump to the specified location in the Flash memory.
In emulation mode, if a breakpoint is encountered while the
KEY is set, the counter that counts the instruction cycles will
be frozen until the breakpoint condition is cleared. If an
interrupt occurs while the key is set, the key will expire
before interrupt service is complete. It is recommended
that the software globally disable interrupts before set-
ting the key and re-enable interrupts on completion of
Boot ROM execution. The Key register is a memory
mapped register. Its format when writing is shown in Table
11.
Bits 7–2: Key value that must be written to set the KEY bit.
Bits 1–0: Don’t care.
Bit 7
R
7
0
0
0
0
0
0
0
0
0
1
Bit 6
TABLE 11. KEY Register Write Format
0
R/W
6
0
0
0
0
1
1
1
1
1
Bit 5
0
KEY When Writing
Bit 4
R/W
1
5
0
0
0
1
0
0
0
0
1
Bit 3
1
TABLE 10. PGMTIM Register Format (Continued)
R/W
Bit 2
4
0
1
1
0
0
0
0
1
0
Register Bit
0
Bit 1
X
R/W
(Continued)
3
1
0
1
1
0
1
1
1
1
Bit 0
X
PGMTIM
R/W
23
2
0
0
0
0
1
0
1
0
1
11.5 FORCED EXECUTION FROM BOOT ROM
When the user is developing a customized ISP routine, code
lockups due to software errors may be encountered. The
normal, and preferred, method to recover from these condi-
tions is to reprogram the device with the corrected code by
either an external parallel programmer or the emulation
tools. As a last resort, when this equipment is not available,
there is a hardware method to get out of these lockups and
force execution from the Boot ROM MICROWIRE/PLUS
routine. The customer will then be able to erase the Flash
Memory code and start over.
The method to force this condition is to shift a 24 bit code
into the G0 pin, using the G2 pin as a shift clock, while Reset
is activated. This special condition will bypass checking the
state of the Flex bit in the Option Register and will start
execution from location 0000 in the Boot ROM. In this state,
the user can input the appropriate commands, using
MICROWIRE/PLUS, to erase the Flash program memory
and reprogram it. If the device is subsequently reset before
the Flex bit has been erased by specific Page Erase or Mass
Erase ISP commands, execution will start from location 0000
in the Flash program memory. The forced entry to
MICROWIRE/PLUS ISP mode will not erase either the Flex
or the Security bit in the Option Register. The Security bit, if
set, can only be erased by a Mass Erase of the entire
contents of the Flash Memory unless under the control of
User ISP routines in the Application Program.
The MICROWIRE/PLUS routine in Boot ROM monitors the
G6 input, waits for it to go low, debounces it, and then
enables the ISP routine. The user may wish to disconnect
other circuitry while RESET, G0, G2 and the MICROWIRE/
PLUS pins are in use for ISP.
The correct sequence to be used to force execution from
Boot ROM is :
1. Apply V
2. Pull RESET Low.
3. Using G2 as a shift clock, shift a value of 5E38AC(hex)
4. Pull RESET High.
5. Pull G6 low and initiate the MICORWIRE/PLUS commu-
into the G0 pin least significant bit first.
nication.
R/W
1
1
0
0
0
0
0
1
1
0
CC
to the device.
R/W
0
0
0
0
0
1
1
0
0
0
CKI Frequency Range
1.025 MHz–2.05 MHz
11.25 MHz–22.5 MHz
6.75 MHz–13.5 MHz
625 kHz–1.25 MHz
3.75 MHz–7.5 MHz
275 kHz–550 kHz
425 kHz–850 kHz
1.5 MHz–3 MHz
2.5 MHz–5 MHz
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