cop8tac9 National Semiconductor Corporation, cop8tac9 Datasheet - Page 44

• Manufacturer Part Number: cop8tac9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
17.0 ACCESS.Bus Interface
17.5 ACB SERIAL DATA REGISTER (ACBSDA)
The ACBSDA register is a byte-wide, read/write shift register
used to transmit and receive data. The most significant bit is
transmitted (received) first and the least significant bit is
transmitted (received) last.
17.6 ACB STATUS REGISTER (ACBST)
The ACBST register is a byte-wide, read-only register that
reports the current ACB status.
17.7 ACB CONTROL STATUS REGISTER (ACBCST)
The ACBCST register is a byte-wide, read/write register that
reports the current ACB status. At reset and when the mod-
ule is disabled, the non-reserved bits of ACBCST are
cleared.
SLVSTP SDAST BER NEGACK RSVD NMATCH MASTER XMIT
SLVSTP
SDAST
BER
NEGACK
RSVD
NMATCH
MASTER
XMIT
(Continued)
7
RSVD
7
7
6
TGSCL
6
5
The Slave Stop bit is set when a Stop
Condition was detected after a slave transfer
(i.e., after a slave transfer in which MATCH
or GCMTCH is set).
The SDA Status bit is set when the SDA
data register is waiting for data (transmit, as
master or slave) or holds data that should be
read (receive, as master or slave)
The Bus Error bit is set when a Start or Stop
Condition is detected during data transfer or
when an arbitration problem is detected.
The Negative Acknowledge bit is set when a
transmission is not acknowledged.
This bit is reserved and will be zero.
The New Match bit is set when the address
byte following a Start Condition, or repeated
starts, causes a match or a global-call
match.
The Master bit indicates that the module is
currently in master mode. It is set when a
request for bus mastership succeeds. It is
cleared upon arbitration loss (BER is set) or
the recognition of a Stop Condition.
The Direction bit is set when the ACB
module is currently in master/slave transmit
mode. Otherwise, it is clear.
5
TSDA
4
4
GCMTCH
DATA
3
3
MATCH
2
2
BB
1
1
BUSY
0
0
0
44
17.8 ACB CONTROL 1 REGISTER (ACBCTL1)
The ACBCTL1 register is a byte-wide, read/write register
that configures and controls the ACB module. At reset and
while the module is disabled (ACBCTL2.ENABLE = 0), the
ACBCTL1 register is cleared.
CLRST NMINTE GCMEN ACK RSVD INTEN
TGSCL
TSDA
GCMTCH The Global Call Match bit is set in slave
MATCH
BB
BUSY
CLRST
NMINTE
7
6
The Toggle SCL bit enables toggling the SCL
signal during error recovery. When the SDA
signal is low, writing 1 to this bit drives the
SCL signal high for one cycle. Writing 1 to
TGSCL when the SDA signal is high is
ignored.
The Test SDA bit samples the state of the
SDA signal. This bit can be used while
recovering from an error condition in which
the SDA signal is constantly pulled low by a
slave that has lost synchronization. This bit is
a read-only bit.
mode when the ACBCTL1.GCMEN bit is set
and the address byte (the first byte
transferred after a Start Condition) is 00.
The Address Match bit indicates in slave
mode when ACBADDR.SAEN is set and the
first seven bits of the address byte (the first
byte transferred after a Start Condition)
matches the 7-bit address in the ACBADDR
register.
The Bus Busy bit indicates the bus is busy. It
is set when the bus is active (i.e., a low level
on either SDA or SCL) or by a Start
Condition. It is cleared when the module is
disabled or a Stop Condition is detected.
The BUSY bit indicates that the ACB module
is:
• Generating a Start Condition
• In Master mode (ACBST.MASTER is set)
• In Slave mode (ACBCST.MATCH or
• In the period between detecting a Start and
The Clear Status bit clears the NMATCH,
BER, NEGACK and SLVSTP bits when 1 is
written to this bit.
The New Match Interrupt Enable controls
whether ACB interrupts are generated on
new matches.
ACBCST.GCMTCH is set)
completing the reception of the address
byte. After this, the ACB either becomes
not busy or enters slave mode. The BUSY
bit is cleared by the completion of any of
the above states, or by disabling the
module. BUSY is a read only bit.
5
4
3
2
STOP
1
START
0