cop8tac9 National Semiconductor Corporation, cop8tac9 Datasheet - Page 46

• Manufacturer Part Number: cop8tac9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
18.0 Memory Map
A8
A9
AA
AB
AC to AF
B0 to B7
B8
B9
BA
BB
BC
BD
BE to BF
C0 to C6
C7
C8
C9
CA
CB to CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3 to E5
E6
ADD REG
Address
ISP Address Register Low Byte
(ISPADLO)
ISP Address Register High Byte
(ISPADHI)
ISP Read Data Register (ISPRD)
ISP Write Data Register (ISPWR)
Reserved
Reserved
ACB Serial Data Register (ACBSDA)
ACB Status Register (ACBST)
ACB Control And Status (ACBCST)
ACB Control Register 1 (ACBCTL1)
ACB Own Address Register (ACBADDR)
ACB Control Register 2(ACBCTL2)
Reserved
Reserved
WATCHDOG Service Register
(Reg:WDSVR)
Port L MIWU Edge Select Register
(Reg:LWKEDG)
Port L MIWU Enable Register
(Reg:LWKEN)
Port L MIWU Pending Register
(Reg:LWKPND)
Reserved
Idle Timer Control Register (ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved
Port J Data Register
Port J Configuration Register
Port J Input Pins (Read Only)
CPU Clock Prescale Register (CLKPS)
Reserved
Flash Memory Write Timing Register
(PGMTIM)
ISP Key Register (ISPKEY)
Reserved
Timer T1 Autoload Register T1RB Lower
Byte
(Continued)
Contents
46
Note: Reading memory locations 70H–7FH will return all ones. Reading
19.0 Instruction Set
19.1 INTRODUCTION
This section defines the instruction set of the COP8 Family
members. It contains information about the instruction set
features, addressing modes and types.
19.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following
features:
• Mostly single-byte opcode instructions minimize program
• One instruction cycle for the majority of single-byte in-
• Many single-byte, multiple function instructions such as
• Three memory mapped pointers: two for register indirect
• Sixteen memory mapped registers that allow an opti-
• Ability to set, reset, and test any individual bit in data
• Register-Indirect LOAD and EXCHANGE instructions
• Unique instructions to optimize program size and
19.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying
memory addresses. Each method is called an addressing
mode. These modes are classified into two categories: op-
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0 to FB
FC
FD
FE
FF
ADD REG
size.
structions to minimize program execution time.
DRSZ.
addressing, and one for the software stack.
mized implementation of certain instructions.
memory address space, including the memory-mapped
I/O ports and registers.
with optional automatic post-incrementing or decrement-
ing of the register pointer. This allows for greater effi-
ciency (both in cycle time and program code) in loading,
walking across and processing fields in data memory.
throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
Address
unused memory locations 80H–83H, 87H–93H will return undefined
data.
Timer T1 Autoload Register T1RB Upper
Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
Timer T1 Autoload Register T1RA Upper
Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
On-Chip RAM Mapped as Register
Contents