x5001pzi Intersil Corporation, x5001pzi Datasheet

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x5001pzi

Manufacturer Part Number
x5001pzi
Description
Cpu Supervisor
Manufacturer
Intersil Corporation
Datasheet
CPU Supervisor
FEATURES
• 200ms power-on reset delay
• Low V
• Selectable nonvolatile watchdog timer
• Long battery life with low power consumption
• 2.7V to 5.5V operation
• SPI mode 0 interface
• Built-in inadvertent write protection
• High reliability
• Available packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
CS/WDI
—Five standard reset threshold voltages
—Adjust low V
—Reset signal valid to V
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—Power-up/power-down protection circuitry
—Watchdog change latch
—8 Ld TSSOP
—8 Ld SOIC
—8 Ld PDIP
V
SCK
CC
SO
special programming sequence
SI
CC
detection and reset assertion
CC
reset threshold voltage using
®
Command
Decode &
1
Register
Control
Logic
CC
Data
= 1V
Data Sheet
V
TRIP
Watchdog
Transition
Detector
1-888-INTERSIL or 1-888-468-3774
+
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
DESCRIPTION
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low V
V
is reset. RESET is asserted until V
operating levels and stabilizes. Five industry standard
V
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The device utilizes Intersil’s proprietary Direct Write
cell for the watchdog timer control bits and the V
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
CC
TRIP
falls below the minimum V
Low Voltage
Generation
Watchdog
Watchdog
Power-on/
Timebase
thresholds are available, however, Intersil’s
All other trademarks mentioned are the property of their respective owners.
Reset &
REset
May 30, 2006
Timer
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
CC
detection circuitry. When
CC
trip point, the system
CC
returns to proper
X5001
FN8125.1
RESET
TRIP

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x5001pzi Summary of contents

Page 1

Data Sheet CPU Supervisor FEATURES • 200ms power-on reset delay • Low V detection and reset assertion CC —Five standard reset threshold voltages —Adjust low V reset threshold voltage using CC special programming sequence —Reset signal valid to V ...

Page 2

Ordering Information PART NUMBER PART MARKING X5001P-2.7 X5001P F X5001PZ-2.7 (Note) X5001P ZF X5001PI-2.7 X5001P G X5001PIZ-2.7 (Note) X5001P ZG X5001S8-2.7 X5001 F X5001S8Z-2.7 X5001 ZF (Note) X5001S8I-2.7 X5001 G X5001S8IZ-2.7 X5001 ZG (Note) X5001V8-2.7 501 F X5001V8Z-2.7 5001 FZ ...

Page 3

Ordering Information (Continued) PART NUMBER PART MARKING X5001V8 501 X5001V8Z (Note) 5001 Z X5001V8I 501 I X5001V8IZ (Note) 5001 IZ X5001PI-4.5A X5001P AM X5001PIZ-4.5A X5001P ZAM (Note) X5001S8-4.5A X5001 AL X5001S8Z-4.5A X5001 ZAL (Note) X5001S8I-4.5A X5001 AM X5001S8IZ-4.5A X5001 ZAM ...

Page 4

PIN CONFIGURATION 8 Ld TSSOP RESET CS/WDI PIN DESCRIPTION Pin Pin (SOIC/PDIP) TSSOP Name 1 1 CS/WDI SCK ...

Page 5

PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5001 activates a power- on reset circuit. This circuit goes active at 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with ...

Page 6

Figure 1. Sample V Reset Circuit TRIP V P Adjust V TRIP Adj. Run Figure 2. Set V Level Sequence (V TRIP SCK SI 03h Figure ...

Page 7

Figure 4. V Programming Sequence TRIP New V Applied = CC Old V Applied + Error CC SPI INTERFACE The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device ...

Page 8

Watchdog Timer Register Watchdog Timer Control Bits The watchdog timer control bits, WD select the watchdog time out period. These nonvola- tile bits are programmed with the set ...

Page 9

Figure 5. Read Watchdog Timer Setting SCK RWDT Instruction SI SO Figure 6. Enable Watchdog Change/Disable Watchdog Change Sequence CS SCK SI SO Figure 7. Write Watchdog Timer Sequence CS 0 SCK SI High ...

Page 10

Figure 8. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation SCK SI SO Figure 9. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation ...

Page 11

ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C ...

Page 12

POWER-UP TIMING Symbol Parameter (2) t Power-up to read operation PUR (2) t Power-up to write operation PUW CAPACITANCE (T = +25° 1MHz Symbol (2) C Output capacitance (SO, RESET) OUT (2) C Input capacitance (SCK, ...

Page 13

Data Output Timing Symbol Parameter f Clock frequency SCK t Output disable time DIS t Output valid from clock low V t Output hold time HO (3) t Output rise time RO (3) t Output fall time FO Notes: (3) ...

Page 14

SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be Will be steady steady May change Will change from LOW from LOW to HIGH to HIGH May change Will change from HIGH from HIGH to LOW to LOW Don’t Care: Changing: Changes State ...

Page 15

Figure 13. CS vs. RESET Timing CS RESET RESET Output Timing Symbol Parameter t Watchdog timeout period, WDO pulse width ...

Page 16

V Programming Parameters TRIP Parameter t V program enable voltage setup time VPS TRIP t V program enable voltage hold time VPH TRIP t V programming CS inactive time PCS TRIP t V setup time TSU TRIP t V hold ...

Page 17

V Supply Current vs. Temperature (I CC Watchdog Timer Watchdog Timer Watchdog Timer Off (V CC 0.55 0.35 -40C 25C Temp (c) V vs. Temperature (programmed at 25°C) TRIP 5.025 5.000 ...

Page 18

Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...

Page 19

Plastic Dual-In-Line Packages (PDIP) D SEATING PLANE MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 A 0.210 0.210 A1 0.015 0.015 A2 0.130 0.130 b 0.018 0.018 b2 0.060 0.060 c 0.010 0.010 D 0.375 0.750 E 0.310 ...

Page 20

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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