x5001pzi Intersil Corporation, x5001pzi Datasheet - Page 8

• Manufacturer Part Number: x5001pzi
• Description: Cpu Supervisor
• Manufacturer: Intersil Corporation

Watchdog Timer Register
Watchdog Timer Control Bits
The watchdog timer control bits, WD
select the watchdog time out period. These nonvola-
tile bits are programmed with the set watchdog timer
(SWDT) instruction.
Write Watchdog Register Operation
Changing the watchdog timer register is a two step
process. First, the change must be enabled by setting
the watchdog change latch (see below). This instruc-
tion is followed by the set watchdog timer (SWDT)
instruction, which includes the data to be written (Fig-
ure 5). Data bits 3 and 4 contain the watchdog settings
and data bits 0, 1, 2, 5, 6 and 7 must be “0”.
Watchdog Change Latch
The watchdog change latch must be SET before a
Write watchdog timer operation is initiated. The
Enable Watchdog Change (EWDC) instruction will set
the latch and the Disable Watchdog Change (DWDC)
instruction will reset the latch (Figure 6). This latch is
automatically reset upon a power-up condition and
after the completion of a valid nonvolatile write cycle.
Table 1. Instruction Set Definition
Note:
Watchdog Control Bits
Instruction Format
7
0
WD1
0
0
1
1
Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
0000 0110
0000 0100
0000 0001
0000 0101
6
0
5
0
WD0
0
1
0
1
WD
4
1
EWDC: Enable Watchdog Change Operation
DWDC: Disable Watchdog Change Operation
SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD
See Watchdog Timer Settings and Figure 7.
RWDT: Read Watchdog Timer Control Bits
8
WD
Watchdog Time Out
3
0
600 milliseconds
200 milliseconds
1.4 seconds
(Typical)
disabled
2
0
0
and WD
1
0
0
0
1
Instruction Name and Operation
,
X5001
Read Watchdog Timer Register Operation
If there is not a nonvolatile write in progress, the read
watchdog timer instruction returns the setting of the
watchdog timer control bits. The other bits are
reserved and will return’0’ when read. See Figure 3.
If a nonvolatile write is in progress, the read watchdog
timer register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a separate read
watchdog timer instruction should be used to determine
the current status of the watchdog control bits.
RESET Operation
The RESET (X5001) output is designed to go LOW
whenever V
point and/or the watchdog timer has reached its pro-
grammable time out limit.
The RESET output is an open drain output and
requires a pull-up resistor.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
– SO pin is high impedance.
– The watchdog change latch is reset.
– The RESET signal is active for t
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A EWDC instruction must be issued to enable a
– CS must come HIGH at the proper clock count in
an active state and receive an instruction.
change to the watchdog timeout setting.
order to implement the requested changes to the
watchdog timeout setting.
CC
1
) (WD
has dropped below the minimum trip
0
)000
PURST
.
May 30, 2006
FN8125.1