ak4396 AKM Semiconductor, Inc., ak4396 Datasheet - Page 14

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ak4396

Manufacturer Part Number
ak4396
Description
Advanced Multi-bit 192khz 24-bit ?? Dac
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V)
Note 18. When the normal/double/quad speed modes are switched, AK4396 should be reset by PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. DSD data transmitting device must meet this time.
Note 21. The AK4396 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,
MS0336-E-00
Parameter
Master Clock Timing
LRCK Frequency
PCM Audio Interface Timing
DSD Audio Interface Timing
Control Interface Timing
Reset Timing
Frequency
Duty Cycle
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
BICK Period
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “↑”
SDATA Hold Time
SDATA Setup Time
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
CCLK Period
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
PDN Pulse Width
BICK “↑” to LRCK Edge
CSN High Time
the AK4396 should be reset by RSTN bit.
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Pulse Width High
SWITCHING CHARACTERISTICS
(Note 21)
(Note 19)
(Note 19)
(Note 20)
(Note 18)
Symbol
tDCKH
tBCKH
tDCKL
tCCKH
tBCKL
tCCKL
dCLK
tDDD
tCSW
fCLK
tBCK
tBCK
tBCK
tDCK
tCCK
tCDH
tBLR
tLRB
tSDH
tCDS
tCSH
tSDS
Duty
tCSS
tPD
fsn
fsd
fsq
- 14 -
1/128fn
1/64fd
1/64fq
1/64fs
min
−20
108
160
160
200
150
150
7.7
40
30
54
45
30
30
20
20
20
20
80
80
50
50
50
50
typ
41.472
max
108
216
60
54
55
20
[AK4396]
Units
2004/08
MHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%

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