ak4396 AKM Semiconductor, Inc., ak4396 Datasheet - Page 20

• Manufacturer Part Number: ak4396
• Description: Advanced Multi-bit 192khz 24-bit ?? Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided (Table 9).
[2] DSD Mode
The external clocks, which are required to operate the AK4396, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4396 is in the normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4396 should be reset by PDN pin = “L” after threse clocks are provided. If the
external clocks are not present, the AK4396 should be in the power-down mode (PDN pin = “L”). After exiting
reset(PDN pin = “L” → “H”) at power-up etc., the AK4396 is in the power-down mode until MCLK is input.
MS0336-E-00
176.4kHz
192.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
LRCK
fs
22.5792
24.5760
128fs
N/A
N/A
N/A
N/A
N/A
Table 9. System Clock Example (Auto Setting Mode @Serial Mode)
DCKS bit
33.8688
36.8640
Table 8. Sampling Speed (Auto Setting Mode @Serial Mode)
192fs
N/A
N/A
N/A
N/A
N/A
0
1
512fs
256fs
128fs
Table 10. System Clock (DSD Mode)
MCLK Frequency
22.5792
24.5760
MCLK
1152fs
256fs
N/A
N/A
N/A
N/A
N/A
512fs
768fs
768fs
384fs
192fs
MCLK (MHz)
33.8688
36.8640
384fs
- 20 -
N/A
N/A
N/A
N/A
N/A
DCLK Frequency
Normal (fs≤32kHz)
Sampling Speed
16.3840
22.5792
24.5760
512fs
N/A
N/A
N/A
N/A
64fs
64fs
Normal
Double
Quad
24.5760
33.8688
36.8640
768fs
N/A
N/A
N/A
N/A
Default
36.8640
1152fs
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
[AK4396]
Normal
Double
Speed
Quad
2004/08