ak4396 AKM Semiconductor, Inc., ak4396 Datasheet - Page 25

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ak4396

Manufacturer Part Number
ak4396
Description
Advanced Multi-bit 192khz 24-bit ?? Dac
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
The AK4396 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 9 shows an example of the system timing at the power-down and power-up.
Notes:
Other:
MS0336-E-00
Power-Down
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge (“↑ ↓”) of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
(6) DZF pins are “L” in the power-down mode (PDN pin = “L”).
After exiting power-down mode (PDN pin: “L”
by a capacitor connected to VCOM pin and the internal resistor of VCOM pin.
The timing example is shown in this figure.
Internal
D/A In
D/A Out
Clock In
MCLK, BICK, LRCK
PDN
External
MUTE
DZFL/DZFR
E.g. C = 10μF
(Digital)
(Analog)
State
1 τ (typ) = 10μF x 0.75kΩ = 7.5ms, 5τ (typ) = 37.5ms
1 τ (max) = 10μF x 0.975kΩ = 9.75ms, 5τ (max) = 48.75ms
(5)
Normal Operation
Figure 9. Power-down/up sequence example
GD
(1)
(3)
(6)
“H”), AOUT pins go to VCOM voltage (VA/2). This time is set
- 25 -
(4)
Mute ON
Power-down
“0” data
Don’t care
(2)
(3)
Normal Operation
GD
(1)
[AK4396]
2004/08

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