ak4370 AKM Semiconductor, Inc., ak4370 Datasheet
ak4370
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ak4370 Summary of contents
Page 1
... ASAHI KASEI 24-Bit 2ch DAC with HP-AMP & Output Mixer The AK4370 is a 24-bit DAC with headphone amplifier. The AK4370 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of power into 16Ω. ...
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... Digital Boost PDN I2C CAD0/CSN Serial I/F SCL/CCLK SDA/CDTI MS0595-E-00 MCKI LIN2 LIN1/IN− DAC (Lch) De- Filter DAC (Rch) RIN1/IN+ RIN2 Figure 1. Block Diagram - 2 - [AK4370] AVDD VSS1 VCOM VCOM LOUT ROUT HDP MUTE HPL Amp HDP MUTE HPR Amp HVDD MUTET 2007/03 ...
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... ASAHI KASEI ■ Ordering Information −30 ∼ +85°C AK4370VN AKD4370 Evaluation board for AK4370 ■ Pin Layout 19 HPR 20 HPL 21 RIN2 22 LIN2 23 RIN1/IN+ 24 LIN1/IN− MS0595-E-00 24pin QFN (0.5mm pitch AK4370VN 10 9 Top View [AK4370] MUTET I2C PDN CSN/CAD0 CCLK/SCL ...
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... These bits are added in the AK4370 These bits are deleted in the AK4370 - 4 - AK4370 2-Stereo Single-ended Input or Full-differential Input 256fs/384fs/512fs/768fs/1024fs, 24.576MHz(max –63dB & +12/+6/0dB 1.5dB step (0 to –30dB) 3dB step (–30 to –63dB) Yes No No ...
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... CSN I Chip Select Pin (3-wire serial mode : I2C pin = “L”) Power-down & Reset 10 PDN I When “L”, the AK4370 is in power-down mode and is held in reset. The AK4370 should always be reset upon power-up. Control Mode Select Pin 11 I2C I “H”: I Mute Time Constant Control pin ...
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... Note 6. When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. When the AK4370 is powered-down, DVDD should be powered-down at the same time or later than AVDD. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier than HVDD ...
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... LIN1L=RIN1L=LIN2L=RIN2L=LIN1R=RIN1R=LIN2R=RIN2R bits = “0” Note 12. Output voltage is proportional to AVDD voltage. Vout = 0.61 x AVDD(typ)@0dBFS. MS0595-E-00 ANALOG CHARACTERISTICS min - - - 1.04 - 0.1 0 =10kΩ) (Note 11 1. [AK4370] L typ max Units - 24 bit −50 −40 dB − 0.3 0.8 dB 200 - ppm/° Ω ...
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... Power-Down Mode (PDN pin = “L”) (Note 14) Note 13. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, HP-Amp no output. PMDAC=PMHPL=PMHPR= “1”, PMLO bit= “0”, AVDD+DVDD+HVDD=4.0mA (typ) @2.4V, 3.8mA (typ) @1.8V. Note 14. All digital input pins are fixed to VSS2. MS0595-E-00 LOUT/ROUT HPL/HPR - 8 - [AK4370] min typ max 100 ...
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... FR FR 20Hz FR 100Hz 1kHz 20Hz FR 100Hz 1kHz 20Hz FR 100Hz 1kHz HPL/HPR/LOUT/ROUT Boost Filter (fs=44.1kHz) 100 Frequency [Hz] Figure 2. Boost Frequency (fs=44.1kHz typ max - 20.0 - 22. ±0. ±0 ± 10. 16.06 - 10. 0.37 - 1000 10000 [AK4370] Units kHz kHz kHz dB dB 1/fs µ 2007/03 ...
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... Note 21. MCKI is connected to a capacitor. (Refer to Figure 38) MS0595-E-00 DC CHARACTERISTICS Symbol min VIH 70%DVDD VIH 80%DVDD VIL VIL VAC VOH (Iout=−200μA) DVDD−0.2 VOL VOL VOL Iin - 10 - typ max - - - - - - 30%DVDD - - 20%DVDD 20%DVDD ± [AK4370] Units Vpp μA 2007/03 ...
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... Units MHz kHz % % 2007/03 ...
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... PDN Pulse Width (Note 29) 2 Note 27 registered trademark of Philips Semiconductors. Note 28. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 29. The AK4370 can be reset by bringing PDN pin = “L” to “H” only upon power up. MS0595-E-00 Symbol min typ ...
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... Timing Diagram 1000pF MCKI Input MCKI LRCK BICK MS0595-E-00 Measurement Point 100kΩ VSS2 VSS2 Figure 3. MCKI AC Coupling Timing 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Figure 4. Clock Timing - 13 - [AK4370] 1/fCLK tACW tACW VAC VIH VIL VIH VIL VIH VIL 2007/03 ...
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... ASAHI KASEI LRCK tBLR BICK SDATA LRCK tMBLR BICK SDATA MS0595-E-00 tLRB tSDS tSDH Figure 5. Serial Interface Timing (Slave Mode) tSDS Figure 6. Serial Interface Timing (Master mode [AK4370] VIH VIL VIH VIL VIH VIL 50%DVDD 50%DVDD tSDH VIH VIL 2007/03 ...
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... Figure 7. WRITE Command Input Timing Figure 8. WRITE Data Input Timing tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure Bus Mode Timing tPD Figure 10. Power-down & Reset Timing - 15 - [AK4370] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH D0 VIL VIH ...
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... AK4370 goes to master mode by changing M/S bit = “1”. When the AK4370 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4370 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state ...
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... ASAHI KASEI The external clocks required to operate the AK4370 in slave mode are MCKI, LRCK and BICK (Figure 12). The master clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter. All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode (PMDAC bit = “ ...
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... Power Down (PMDAC bit = “0”) Input or fixed to “L” or “H” externally Fixed to “L” or “H” externally Fixed to “L” or “H” externally Table 4. Clock Operation in Slave mode DR, S/N (BW=20kHz, A-weight) MCKI fs=8kHz 56dB 768fs/1024fs 75dB - 18 - fs=16kHz 75dB 90dB [AK4370] 2007/03 ...
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... In all modes, the serial data is MSB first and 2’s complement format. When master mode and BICK=32fs(BF bit = “0”), the AK4370 cannot be set to Mode 1, Mode 2 and Mode4. Mode ...
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... Rch Don’t 0 care Don’ care Don’ care Rch Don’ care Don’ care Don’ care [AK4370 2007/03 ...
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... Digital Attenuator The AK4370 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 7). At DATTC bit = “1”, ATTL7-0 bits control both channel’s attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the left channel level and ATTR7-0 bits control the right channel level ...
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... The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and it is returned to the ATT level by the same cycle. MS0595-E-00 ATS bit (1) GD (2) Figure 17. Soft Mute Function - 22 - ATS bit (1) (3) GD [AK4370] 2007/03 ...
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... ASAHI KASEI ■ De-emphasis Filter The AK4370 includes a digital de-emphasis filter (tc = 50/15μs), using an IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 9). DEM1 bit ■ Bass Boost Function By controlling the BST1-0 bits, a low frequency boost signal can be output from DAC. The setting value is common for both channels (Table 10) ...
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... VSS1, some pop noise may occur. MS0595-E-00 Table 12. Headphone-Amp Rise/Fall Time = 70k x 1μ = 70ms (typ 60k x 1μ = 60ms (typ (1) ( 70k x C (typ) 60k x C (typ (4) (3) [AK4370] = 70k x r 2007/03 ...
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... Wired OR with External Headphone-Amp > When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, Headphone-amp is powered-down and HPL/R pins are pulled-down to VSS1 by 200kΩ (typ). In this setting available to connect headphone-amp of AK4370 and external single supply headphone-amp by “wired OR”. PMVCM ...
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... DAC path is +6.95dB (typ). DH 100k(typ 100k(typ − 100k(typ 100k(typ − Figure 21. Summation circuit for HPL/R output - 26 - [AK4370 200k 1.11R H − HPL pin + HP-Amp 1.11R H − HPR pin + HP-Amp 2007/03 ...
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... MUTE MUTE - 27 - [AK4370] HPG1-0 bits = “00” STEP 0dB Default −1.5dB −3dB −4.5dB : 1.5dB : −27dB −28.5dB −30dB −33dB −36dB : : 3dB −57dB −60dB − ...
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... RIN2 pin RIN2R bit DAC Rch DARR bit MS0595-E- 200k 100k(typ − 100k(typ − Figure 22. Summation circuit for stereo line output - − LOUT pin + − ROUT pin + [AK4370 2007/03 ...
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... LOG bit = “1” ATTS3-0 (DAC Only) FH +6dB EH +4dB DH +2dB CH 0dB : : : : −22dB 1H −24dB 0H x MUTE - 29 - Figure 21 HPL/R pins − LOUT pin + − ROUT pin + LOG bit = “0” 0dB −2dB −4dB −6dB : : −28dB −30dB MUTE Default [AK4370] 2007/03 ...
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... AVDD. When AVDD and HVDD are supplied separately, AVDD should be powered-down at the same time or later than HVDD. MS0595-E-00 Don’t care Don’t care Normal Operation PD (5) >2ms FFH(0dB) 00H(MUTE) (8) (9) (8) GD (9) 1061/fs (7) = 70ms(typ 60ms(typ [AK4370] Don’t care Normal Operation PD (4) >0s (5) >2ms FFH(0dB) 00H(MUTE) (8) (9) (8) (9) (6) (7) (10) 2007/03 ...
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... Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499μs@fs=44.1kHz). (8) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). MS0595-E-00 (5) (4) >0s Normal Operation FFH(0dB) 00H(MUTE) 0FH(0dB) (7) GD (8) 1061/fs (7) (8) ( Don’t care Don’t care PD Normal Operation FFH(0dB) (7) (8) (6) (6) (Hi-Z) [AK4370] 2007/03 ...
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... PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the LIN1HL, LIN2HL, RIN1HR and RIN2HR bits should be changed to “0”. MS0595-E-00 (3) >0s (5) >2ms (4) (6) (7) = 70ms(typ 60ms(typ Don’t care (5) >2ms (Hi-Z) (6) [AK4370] 2007/03 ...
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... PMLO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LIN1L, LIN2L, RIN1R and RIN2R bits are changed to “1”. (6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0595-E-00 (3) >0s (5) >2ms (4) 0FH(0dB) ( Don’t care (5) >2ms (Hi-Z) (6) (6) (Hi-Z) [AK4370] 2007/03 ...
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... CSN 0 CCLK CDTI C1 C0 MS0595-E- R C1-C0: Chip Address (Fixed to “01”) R/W: READ/WRITE (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data Figure 28. 3-wire Serial Control I/F Timing - [AK4370] 2007/03 ...
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... The second byte consists of the control register address of the AK4370. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 31). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 32) ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4370. After a transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the writing cycle after receiving the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 13H prior to generating a stop condition, the address counter will “ ...
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... MASTER S START CONDITION SDA SCL MS0595-E-00 S Figure 35. START and STOP Conditions 2 1 Figure 36. Acknowledge on the I data line change stable; of data data valid allowed Figure 37. Bit Transfer on the stop condition not acknowledge acknowledge 8 clock pulse for acknowledgement 2 C-Bus 2 C-Bus [AK4370] 9 2007/03 ...
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... RIN2HR RIN2HL LIN1HR ATTH3 ATTH2 ATTH1 0 RIN2R RIN2L LIN1R 0 L2M L2HM L1M LDIFH [AK4370] D0 PMVCM 0 0 DIF0 DEM0 ATTL0 ATTR0 DALHL DALL ATTS0 RIN1HL ATTH0 RIN1L L1HM LDIF 0 0 2007/03 ...
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... When PMVCM, PMDAC, PMHPL, PMHPR and PMLO bits are “0”, all blocks are powered-down. The register values remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), PDN pin should be “L”. MS0595-E- PMLO MUTEN RD RD R/W R [AK4370 PMHPR PMHPL PMDAC PMVCM R/W R/W R 2007/03 D0 R/W 0 ...
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... M/S MCKAC RD RD R/W R MONO1 MONO0 BCKP RD R/W R LRP DIF2 DIF1 R/W R/W R [AK4370 DIF0 R/W 0 2007/03 ...
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... MS0595-E- ATS DATTC LMUTE SMUTE R/W R/W R/W R ATTL7 ATTL6 ATTL5 ATTL4 ATTR7 ATTR6 ATTR5 ATTR4 R/W R/W R/W R BST1 BST0 DEM1 R/W R/W R ATTL3 ATTL2 ATTL1 ATTR3 ATTR2 ATTR1 R/W R/W R [AK4370] D0 DEM0 R ATTL0 ATTR0 R/W 0 2007/03 ...
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... ON LIN2HR: Input signal to LIN2 pin is added to the right channel of the headphone-amp. 0: OFF (Default HPG1-0: DAC HPL/R Gain (Note 18) Default: “00”: +0.95dB MS0595-E- HPG1 HPG0 LIN2HR LIN2HL R/W R/W R/W R [AK4370 RIN1HR LIN1HL DARHR DALHL R/W R/W R 2007/03 D0 R/W 0 ...
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... Setting of ATTS3-0 bits is enabled at LMUTE bit is “0”. MS0595-E- LOG LIN2R LIN2L RD R/W R/W R [AK4370 RIN1R LIN1L DARR DALL R/W R/W R/W R ATTS3 ATTS2 ATTS1 ATTS0 R/W R/W R/W R 2007/ ...
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... HPZ: Headphone-Amp Pull-down Control 0: Shorted to GND (Default) 1: Pulled-down by 200kΩ (typ) MS0595-E- HPZ HMUTE ATTH4 RD R/W R/W R RIN2HR RIN2HL LIN1HR R/W R/W R ATTH3 ATTH2 ATTH1 R/W R/W R [AK4370] D0 RIN1HL R ATTH0 R/W 0 2007/03 ...
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... [AK4370 RIN2R RIN2L LIN1R RIN1L R/W R/W R/W R L2M L2HM L1M L1HM R/W R/W R/W R LDIFH LDIF RD RD ...
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... All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not be left floating. - When the AK4370 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to “1”. Therefore, a 100kΩ pull-up resistor should be connected to the LRCK and BICK pins of the AK4370. ...
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... System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4370 as possible, with the small value ceramic capacitors being the nearest. ...
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... Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Package & Lead frame material Package molding compound: Epoxy Lead frame material: Lead frame surface treatment: Solder (Pb free) plate MS0595-E-00 PACKAGE 12 7 0.23 ± 0. 2.4 ± 0. Exposed Pad 24 0.40 ± 0 PIN #1 ID 0.10 M (0. [AK4370] 2007/03 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0595-E-00 MARKING 4370 XXXX 1 XXXX: Date code (4 digit) Revision History Reason Page Contents First Edition IMPORTANT NOTICE - 49 - [AK4370] 2007/03 ...