ak4370 AKM Semiconductor, Inc., ak4370 Datasheet - Page 30

• Manufacturer Part Number: ak4370
• Description: 24-bit 2ch Dac With Hp-amp & Output Mixer
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
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1) DAC → HP-Amp
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes “H”.
(3) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
(4) DALHL and DARHR bits should be changed to “1” after PMVCM and PMDAC bit is changed to “1”.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
(8) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µs@fs=44.1kHz).
(9) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(10) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
MS0595-E-00
Power-Up/Down Sequence
Clock Input
PMDAC bit
DAC Internal
SDTI pin
PMHPL,
PMHPR bits
MUTEN bit
ATTL7-0
ATTR7-0 bits
HPL/R pin
Power Supply
PDN pin
PMVCM bit
DALHL,
DARHR bits
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied.
can be stopped. The headphone-amp can operate without these clocks.
is 2.2μF) after the DALHL and DARHR bits are changed to “1”
VCOM/2 is t
VCOM/2 is t
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the DALHL and
DARHR bits should be changed to “0”.
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or later than
AVDD. When AVDD and HVDD are supplied separately, AVDD should be powered-down at the same time or later
than HVDD.
State
r
f
Figure 24. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
= 70k x C(typ). When C=1μF, t
= 60k x C(typ). When C=1μF, t
Don’t care
PD
(1)
>150ns
00H(MUTE)
(2) >0s
(3)
(6)
(4) >0s
(5) >2ms
(8) GD (9) 1061/fs
FFH(0dB)
Normal Operation
r
f
= 70ms(typ).
= 60ms(typ).
(8) (9)
- 30 -
(7)
00H(MUTE)
Don’t care
Don’t care
PD
(6)
(4) >0s
(5) >2ms
Normal Operation
(8) (9)
FFH(0dB)
(8) (9)
00H(MUTE)
(7)
Don’t care
[AK4370]
PD
2007/03
(10)