wm8974gefl-v Wolfson Microelectronics plc, wm8974gefl-v Datasheet - Page 52

• Manufacturer Part Number: wm8974gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8974
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Table 48 Clock Control
LOOPBACK
COMPANDING
Note that the setting MCLKDIV=000 and BCLKDIV=000 must not be used simultaneously.
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
The WM8974 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
R6
Clock generation
control
REGISTER
ADDRESS
0
4:2
7:5
8
BIT
MS
BCLKDIV
MCLKDIV
CLKSEL
LABEL
0
000
010
1
DEFAULT
Sets the chip to be master over FRAME and
BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs
generated by the WM8974 (MASTER)
Configures the BCLK and FRAME output
frequency, for use when the chip is master
over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Sets the scaling for either the MCLK or PLL
clock output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
PD, Rev 4.5, September 2008
DESCRIPTION
Production Data
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