wm8974gefl-v Wolfson Microelectronics plc, wm8974gefl-v Datasheet - Page 68

• Manufacturer Part Number: wm8974gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8974
w
6 (06h)
7 (07h)
8 (08h)
REGISTER
ADDRESS
2:1
0
8
7:5
4:2
1
0
8:4
3:1
0
8:6
5:4
BIT
ADC_COMP
LOOPBACK
CLKSEL
MCLKDIV
BCLKDIV
MS
SR
OPCLKDIV
LABEL
00
1
000
00
0
010
0
0
00000
000
0
000
DEFAULT
ADC companding
00=off
01=reserved
10=µ-law
11=A-law
Digital loopback function
0=No loopback
1=Loopback enabled, ADC data output is fed directly into
DAC data input.
Controls the source of the clock for all internal operation:
0=MCLK
1=PLL output
Sets the scaling for either the MCLK or PLL clock output
(under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Configures the BCLK and FRAME output frequency, for use
when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Reserved
Sets the chip to be master over FRAME and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs generated by the
WM8974 (MASTER)
Reserved
Approximate sample rate (configures the coefficients for the
internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Reserved
Reserved
PLL Output clock division ratio
00=divide by 1
01=divide by 2
10=divide by 3
11=divide by 4
DESCRIPTION
PD, Rev 4.5, September 2008
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
Interfaces
Audio Sample
Rates
General Purpose
Input Output
Production Data
REFER TO
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