wm8974gefl-v Wolfson Microelectronics plc, wm8974gefl-v Datasheet - Page 58

• Manufacturer Part Number: wm8974gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8974
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RESETTING THE CHIP
POWER SUPPLIES
2-WIRE SERIAL CONTROL MODE
The WM8974 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8974).
The WM8974 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8974, then the WM8974 responds by pulling SDIN low on the next clock pulse
(ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the
WM8974 returns to the idle condition and wait for a new start condition and valid address.
During a write, once the WM8974 has acknowledged a correct address, the controller sends the first
byte of control data (B15 to B8, i.e. the WM8974 register address plus the first bit of register data).
The WM8974 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8974 acknowledges again by pulling SDIN low.
Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the WM8974 returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the device jumps to the idle condition.
In 2-wire mode the WM8974 has a fixed device address, 0011010.
The WM8974 can be reset by performing a write of any value to the software reset register (address
0 hex). This will cause all register values to be reset to their default values. In addition to this there
is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the
device is powered up.
The WM8974 can use up to four separate power supplies:
AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and
mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on
overall power consumption (except for power consumed in the headphone). A large AVDD slightly
improves audio quality.
SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output
drivers. SPKVDD can range from 2.5V to 5.5V. SPKVDD can be tied to AVDD, but it requires
separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD,
louder headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower
than AVDD (or 1.5 x AVDD for BOOST mode), the output signal may be clipped.
DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.
DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for
DCVDD is DGND, which is shared with DBVDD.
DBVDD Can range from 1.71V to 3.6V. DBVDD return path is through DGND.
It is possible to use the same supply voltage for all four supplies. However, digital and analogue
supplies should be routed and decoupled separately on the PCB to keep digital switching noise out
of the analogue signal paths.
Figure 33 2-Wire Serial Control Interface
SCLK
SDIN
START
DEVICE ADDRESS
(7 BITS)
RD / WR
BIT
(LOW)
ACK
register address and
CONTROL BYTE 1
1st register data bit
(BITS 15 TO 8)
(LOW)
ACK
CONTROL BYTE 1
remaining 8 bits of
(BITS 7 TO 0)
register data
PD, Rev 4.5, September 2008
(LOW)
ACK
Production Data
STOP
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